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The PCB design process has traditionally been done in silos. One group creates the design intent (schematic), another group implements the logic on the PCB, and yet another group does some checking of the design using analysis tools. This traditional approach has run into a number of problems.
The first problem was that prototypes were showing up in the lab that did not work due to complicated signal and power integrity problems not found by the analysis tools. But even when the analysis team equipped themselves with sophisticated analysis tools, the back-and-forth between silos or lack of time in the schedule tended to create chaos as design deadlines loomed.
Today, modern PCB design methodology offers a more team-oriented solution. With a front-to-back constraint driven approach that enables all groups to get involved with signal and power integrity, many potential problems are either avoided or found early in the design process. With first order problems removed, the analysis team, with their sophisticated tools, is better positioned to focus on design sign-off so prototypes come back working the first time.
This article is focused on how each part of that design team can get out of their silo and work cooperatively. Using a common constraint manager, each group can utilize their varying levels of expertise to ferret out signal and power integrity problems.
For teams seeking to break out of their historic silos, tools can help by providing a certain amount of integration. One way that can happen is by having a constraint system integrated with your SI system at all stages of your design process. While decisions are being made for physical partitioning, component/IP selections, and power requirements, pre-layout analysis can help define your solution space and corresponding electrical constraints. This early analysis as part of a well-executed constraint driven flow saves time and prevents issues from propagating down to SI signoff.
Topology analysis is usually what comes to mind when thinking of pre-layout analysis and is an ideal environment for what-if analysis. Here you can start from scratch or by extracting nets from design data in the schematic or layout. In either case you can quickly build a representation of the major interfaces in the design. Models for active devices should be as accurate as possible and interconnect can be estimated or parameterized and swept.
To read this entire article, which appeared in the July 2016 issue of The PCB Design Magazine, click here.