Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue Waves


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In the dark ages of power distribution design, the typical advice was to use a bulk capacitor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed [1]. Using a target impedance, designers had a metric and a design goal to guarantee that the voltage transients stay within specified limits.

Strictly speaking, the target-impedance concept is valid only for flat self-impedance profiles; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst-case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves [2]. But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbitrary impedance profile. 

The target impedance concept assumes that the power distribution network is hit by a series of current steps, each current step having a magnitude of DI and fastest transition time of ttr. If up to the BW bandwidth of the excitation the PDN impedance is Ztarget, the resulting voltage transients are within the DV limits.

To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.

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