# Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue Waves

In the dark ages of power distribution design, the typical advice was to use a bulk capacitor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed [1]. Using a target impedance, designers had a metric and a design goal to guarantee that the voltage transients stay within specified limits.

Strictly speaking, the target-impedance concept is valid only for flat self-impedance profiles; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst-case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves [2]. But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbitrary impedance profile.

The target impedance concept assumes that the power distribution network is hit by a series of current steps, each current step having a magnitude of DI and fastest transition time of ttr. If up to the BW bandwidth of the excitation the PDN impedance is Ztarget, the resulting voltage transients are within the DV limits.

To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.

## ‘The Trouble with Tribbles’

06/17/2021 | Dana Korf, Korf Consultancy
The original Star Trek series came into my life in 1966 as I was entering sixth grade. I was fascinated by the technology being used, such as communicators and phasers, and the crazy assortment of humans and aliens in each episode. My favorite episode is “The Trouble with Tribbles,” an episode combining cute Tribbles, science, and good/bad guys—sprinkled with sarcastic humor.

## IPC-2581 Revision C: Complete Build Intent for Rigid-Flex

04/30/2021 | Ed Acheson, Cadence Design Systems
With the current design transfer formats, rigid-flex designers face a hand-off conundrum. You know the situation: My rigid-flex design is done so now it is time to get this built and into the product. Reviewing the documentation reveals that there are tables to define the different stackup definitions used in the design. The cross-references for the different zones to areas of the design are all there, I think. The last time a zone definition was missed, we caused a costly mistake.

## Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.