Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue Waves

Reading time ( words)

In the dark ages of power distribution design, the typical advice was to use a bulk capacitor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed [1]. Using a target impedance, designers had a metric and a design goal to guarantee that the voltage transients stay within specified limits.

Strictly speaking, the target-impedance concept is valid only for flat self-impedance profiles; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst-case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves [2]. But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbitrary impedance profile. 

The target impedance concept assumes that the power distribution network is hit by a series of current steps, each current step having a magnitude of DI and fastest transition time of ttr. If up to the BW bandwidth of the excitation the PDN impedance is Ztarget, the resulting voltage transients are within the DV limits.

To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.


Suggested Items

Real Time with... DesignCon: Mentor Partners with Sintecs on EU Project

02/16/2018 | Real Time with DesignCon
During DesignCon 2018, Guest Editor Kelly Dack interviewed Sintecs' CEO Evert Pap and system architect Hans Klos in the Mentor booth. Sintecs used Mentor's software tools to design the dReDBox, a virtual prototype project funded by the European Union.

Who Really Owns the PCB Layout? Part 2

02/07/2018 | Paul Taubman, Nine Dot Connects
In Part 1 of this series, Paul Taubman made the bold statement that the PCB layout is just as much a mechanical effort as it is an electrical one. In Part 2, he threads the needle, explaining why he believes that a PCB truly a mechatronic design, and why mechanical engineers may be more prepared to take on the PCB layout.

EMA Cloud Lined with Capability

02/05/2018 | Real Time with DesignCon
Editor Kelly Dack speaks with EMA Design Automation Marketing Manager Chris Banton about the company's new free cloud-based OrCAD schematic capture tool, OrCAD's design constraint manager, and the Sigrity electrical rule checker.

Copyright © 2018 I-Connect007. All rights reserved.