Systematic Estimation of Worst-Case PDN Noise: Target Impedance and Rogue Waves


Reading time ( words)

In the dark ages of power distribution design, the typical advice was to use a bulk capacitor and one 0.1uF bypass capacitor for every power pin on the digital circuit. This was very unscientific, but served the industry reasonably well in low-density and low-speed circuits. As the designs got more demanding, the target impedance concept was developed [1]. Using a target impedance, designers had a metric and a design goal to guarantee that the voltage transients stay within specified limits.

Strictly speaking, the target-impedance concept is valid only for flat self-impedance profiles; however, most of our practical designs do not have that luxury. With non-flat impedance profiles, the noise is different. Surprisingly and counterintuitively, keeping the same maximum impedance, the more we deviate from the flat impedance by pushing the impedance down in certain frequency ranges, the higher the worst-case transient noise becomes. This raises the question how to do a systematic design and also gives rise to speculations about rogue waves [2]. But there is a systematic, fast and efficient way of calculating the worst-case noise for any arbitrary impedance profile. 

The target impedance concept assumes that the power distribution network is hit by a series of current steps, each current step having a magnitude of DI and fastest transition time of ttr. If up to the BW bandwidth of the excitation the PDN impedance is Ztarget, the resulting voltage transients are within the DV limits.

To read this entire article, which appeared in the December 2015 issue of The PCB Design Magazine, click here.

Share


Suggested Items

Fadi Deek Discusses Mentor’s New Power Integrity eBook

04/22/2018 | Andy Shaughnessy, Design007 Magazine
At DesignCon 2018, I ran into Mentor’s Fadi Deek, the author of both of Mentor’s I-Connect007 eBooks: the newest, "The Printed Circuit Designer’s Guide to Power Integrity by Example," and their first book, "The Printed Circuit Designer’s Guide to Signal Integrity by Example." We sat down and discussed how the idea for the books came about, as well as some of the power integrity challenges facing PCB designers and engineers.

Mentor’s HyperLynx Automates SERDES Channel Design

04/09/2018 | Andy Shaughnessy, Design007 Magazine
Mentor recently released the newest version of its HyperLynx signal integrity software. This version may be the first SI tool in the industry to fully automate SERDES design channel validation. I spoke recently with Chuck Ferry, product marketing manager with Mentor, about the new HyperLynx and some of the new serial link design capabilities that customers have been demanding.

Julie Ellis: TTM’s Interface Between Designer and Fabricator

04/04/2018 | Barry Matties, Publisher, I-Connect007
As a field application engineer for TTM, Julie Ellis sees the problems that can occur between circuit board designers and manufacturers. Barry Matties spoke with Julie at the AltiumLive event in Munich about the age-old problem of throwing designs “over the wall,” the trend towards HDI, and what advice she would give new designers.



Copyright © 2018 I-Connect007. All rights reserved.