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Optimizing large pin-count FPGAs is challenging. Manual optimization can take days and result in reduced quality.
This new video from Mentor Graphics shows how signal pin assignments can be automatically optimized between multiple FPGAs on the PCB while respecting pin-specific rules and constraints. Reduce the number of routing layers, minimize crossovers and overall trace lengths on the PCB, and reduce signal integrity issues for higher completion rates and shorter FPGA route times.
To watch this video, click here.
Pete Starkey, I-Connect007
Believing that I knew a bit about signal integrity and controlled impedance, I was pleased to take the opportunity to connect with an educational webinar that I hoped would extend my knowledge. In the event I was surprised at how little I actually knew, and the webinar was an excellent learning opportunity. The webinar was introduced and expertly moderated by Anna Brockman of Phoenix Contact in Germany.
Steve Hageman, Analog Home
Does putting a ground pour on PCB signal layers make the isolation better or worse? It can go either way, but with the proper knowledge and application, this technique will improve your designs. In this article, I’ll discuss how to simulate trace-to-trace isolation with true electromagnetic simulation software. We’ll also cover a variety of rules of thumb that can help you stay away from trouble.
Andy Shaughnessy, Design007 Magazine
I recently spoke with Heidi Barnes and Stephen Slater, both engineers with Keysight Technologies, about their presentations at this year’s virtual AltiumLive. They discussed ways to avoid signal and power integrity challenges later by following simple board design practices early on, how SI and PI are interconnected, and why the return path must be more than an afterthought in high-speed designs.