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Design for Manufacturing: The Hidden Economy of HDI
September 4, 2013 |Estimated reading time: 1 minute
When I mentioned during our regular Wednesday meeting that HDI would be the focus of an upcoming issue of The PCB Design Magazine, our vice president of manufacturing, Steve Arobio, and Atar Mittal, who directs design and assembly, insisted this column must explain, once and for all, the economy of buried vias.
“The common wisdom,” Steve said, “is more laminations equal more cost, and it’s really hard to break that myth.”
Atar and Steve are too tactful to call any designs simpleminded, but I can tell you that they see attempts week in and week out, and to steer clear of buried vias no matter the results; sometimes the results can’t be manufactured.
“Why, I ask customers, would you simply add layer after layer and make holes smaller and smaller as your circuit designs become more complex? Why would you gamble on high via aspect ratios and tight hole-to-copper clearance?” Steve wondered. “Why not turn to a blind-and-buried via architecture and achieve 8-mil hole-to-copper clearances, instead of 3 or 4 mils; aspect ratios that are 8:1 instead of 20:1; and use fewer layers?”
Yes, multiple laminations cost more than a single lamination, but that’s merely one factor to consider in a thorough cost-benefit analysis when developing a stack-up. First, let’s distinguish between prototype fabrication and production runs.Read the full column here.Editor's Note: This column originally appeared in the May 2013 issue of The PCB Design Magazine.