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Electronic Interconnection Files - Number 6 -- Breaking the Memory Bottleneck
December 17, 2005 |Estimated reading time: 3 minutes
Processors and memory have been inextricably linked since the dawn of modern electronic computing and for a substantial period of their shared existence there has existed the so-called "memory bottleneck". The memory bottleneck can perhaps be best characterized as the performance disparity between the CPU and the memory bus and it is commonly a major limiting factor to overall system performance. While in former times with older computers the processor ran at about the same speed as the memory bus, in newer computer systems the processor chip is running at rates up to 5 to 10 times the speed of the memory. While local system cache memory, which is much faster than the main memory, helps to ameliorate the problem to some degree by allowing the processor to get more done with less waiting, there is still a delay when accessing main memory and this bottleneck has remained a problem. <?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" />
Once again, however, it appears that by careful use and modification of the electronic interconnection another common problem can be overcome. It thus appears possible that one can avoid having to change the native memory interface by using a novel controller and buffering scheme, facilitated by clean electronic interconnection channels, which can push data-transfer rates for standard SDRAMs to up to 3.2 Gbps/pin. Moreover, it appears that data rates up to 12.8 Gbps/pin are possible for first-generation double-data-rate (DDR) SDRAMs. All of this is possible by use of a clean electronic channel, a modified memory controller and a MUX/DEMUX (multiplexer/demultiplexer) buffer to effect a comprehensive solution. The new approach has been described as a Chaniplexer, a concept forwarded by SiliconPipe for the industry to consider. The Chaniplxer chip set solution is nicely suited to desktop and server systems and it can be used with standard dual inline-memory modules (DIMMs), though improvements to the basic idea will likely yield new options. The Chaniplexer system has a controller connected to the processor or to the DRAM controller's address/data bus, which converts the parallel data into multiple differential serial channels, which are then connected to the MUX/DEMUX chips, positioned between the DIMM connector and the differential signal traces.
Differential signals have greater immunity to noise than standard parallel buses, adding flexibility in PCB layout relative to the DRAM chips proximity to the memory controller. The solution does require some PCB modifications to the existing memory-controller data path, however, no changes are required for the processor or chip set, nor are changes required to the memory DIMMs.
It is believed that when used with existing DIMMs and system logic, the Chaniplexer can be implemented with systems containing word widths of up to 128 bits and support as many as 32 DIMMs. When used with DDR DIMMs, data rates start at 12.8 Gbits/s and can scale to over 20 Gbits/s. Where even more demanding or higher performance is required another solution is possible, which requires a redesigned DIMM and silicon modification. The solution has been tagged the Seriplexer and it will allow the system developer/user to achieve data rates of up to 24 Gbits/s per pin and even beyond.
The serial channels eliminate signal disruptions between the memory controller and the memory devices which it services. In the Seriplexer design scheme, serial channels will transfer bit streams at data rates starting at 3.2 Gbps and scaling up to 8 Gbps and beyond, depending on the memory interface used.
The Seriplexer scheme requires custom DIMMs optimized for the approach. With it, data transfers should hit 24 Gbits/s and higher and it is believed that the Seriplexer concept will have virtually no scaling limits, so it can work in systems that concurrently employ different memory technologies.
In summary, the memory bottleneck continues to exist but only because the present approach to memory access remains basically the same. Solutions are ready for those willing to make the adjustments to some new ways of considering interconnections.
References:
1) http://www.elecdesign.com/Articles/ArticleID/7169/7169.html