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A Design of Experiments for Gigabit Serial Backplane Channels
December 10, 2008 |Estimated reading time: Less than a minute
Today's backplane environment presents challenges for high-speed digital designers. Trade-offs between signal integrity performance, cost and reliability must be made to achieve the proper architecture for a robust physical layer channel. This paper discusses an in-depth design of experiments using combinations of three high-speed connectors, three dielectric materials and three channel lengths. Written by Mike Resso of Agilent Technologies, Jack Carrel of Xilinx and Bill Dempsey of Redwire Enterprises, it was presented at DesignCon 2009.
Click here to read.