Constraint Entry: Helping Hands Make Light Work
August 27, 2008 |Estimated reading time: 9 minutes
The functions and capacity of electronic systems have dramatically increased over the over the past couple of decades. In telecommunications, military/aerospace or consumer products, the functionality crammed onto the silicon - and therefore the PCB - is continually growing.
To cope with the intensive graphics and handle the number-crunching, the design team must develop systems that deliver the required performance: increased data rates, smaller form factors, etc. These demands on system performance lead to one thing - the majority of nets on a design are no longer simple connections from point A to point B - they have become signal propagation paths that may have a profound direct affect on the quality of the signal.
This shift in design requirements has, in turn, lead to a shift in design approach. Much more attention must be paid to the high-speed aspects of the PCB layout, taking into consideration the effects of the board stackup, placements, and especially the routing of the traces. These factors all affect the performance of the board and to this end they have to be characterized and then controlled. Before this shift in design emphasis, the maxim of "Make it a short as possible" held true, especially when the design had only a handful of critical nets. But this attitude is no longer relevant when a design has 4,000 nets that must be considered for high-speed issues, and a designer must ensure design intent.
Another aspect that has complicated the design process is the very tight design tolerances that must be adhered to with the new protocols that are commonly used by companies today. In many cases the designer must perform a series of signal integrity simulations to determine design marginality. It is no good if the design only functions when all the devices are at typical values or the moon is in the house of Orion! The design must function across the complete spectrum of component operation and environment. Also, in many cases the designer must allow for the variances in operational parameters due to component multi-sourcing, i.e., manufacturer A has different characteristics than manufacturer B. The end result is an explosion in the number of constraints required to ensure the design functions to specification.
Rules Entry Evolution
Constraint (rules) entry was not always at the forefront of the design process. Twenty years ago the majority of designs contained only a handful of nets that could be considered sensitive to the physical layout, and these were mainly confined to the clocks, RF, or analog content. Usually the engineer would sit with the layout designer and help place and route these critical sections, as illustrated in Figure 1. Although this was very user-intensive it did not generally take a great deal of time because the number of nets involved was typically small. Also, the designers could concentrate on making these nets as short as possible, because the other non-critical nets could be traced around them. But as designs have become more and more complex, this approach is longer feasible. Today many engineers enter the rules into integrated front-end constraint systems.
Figure 1: In the past, constraints were provided to the layout designer in inefficient ways, such as orally, on random scraps of paper, or with a tedious spreadsheet.
For many years, companies split the schematic capture of the board design between multiple engineers. At first this simply allowed for parallel design, but as the designs have become more complex, there has been a growing need to specialize in one area of the PCB. And today the engineer has complete responsibility for the protocol - from schematic capture to constraint definition through to circuit simulation and verification.
This need for specialization is highlighted by the fact that many PCB systems contain a mixture of standard design protocols - DDR memory, PCI-X, or SERDES interface and custom circuitry. The standard protocols are normally supplied with complex timing information as well as a set of extensive layout guidelines to ensure that the system functions within acceptable parameters. Although these guidelines precisely define the required routing, the designer should perform signal integrity simulation to take into account the precise layout environment, i.e., tracking the actual stackup and location of other systems.
The constraints for the remaining custom circuitry are normally developed using pre-layout signal integrity analysis. The net is extracted directly from the constraint database in an integrated system and displayed in the simulation environment. Users can then explore the effects that the topology, impedance and board stackup have upon the signal quality and timing by performing a series of simulations. Once these have been completed, an operation envelope can be determined and a constraint template can be created and passed back to the constraints system and applied to the relevant nets.
Constraint Entry Impact
The amount of time spent on design constraint entry has also increased with the number of constraints. The previous practices of guiding the layout engineer through the layout or passing him the constraints on scraps of paper no longer apply.
With advances in clock speed, system timing constraints are firmly in the sub-nanosecond world. This means that even the connector pin length must be taken into account when calculating the overall timing. In many cases, there is a mismatch between lengths of those connect pins, which has led engineers to create spreadsheets to allow for this disparity by calculating the exact minimum and maximum lengths for the nets. This process is both expensive and potentially error-prone.
Even taking into account the number of automated constraint entry techniques available, such as differential pair definition and constraint templates, constraint entry is firmly on the critical path.
Constraint Collaboration
Although multiple engineers have been able to enter schematics concurrently for some time, this is not true of constraints. Constraint systems have traditionally been structured to allow only a serial entry process, but the serial process is no longer efficient in this design environment, as many designers can testify. It is very rare that designers have all the data they need when they start entering the constraints. This means that they either stop entering data while they find it or they pass the baton to another designer and then wait until the baton is passed back. This leads to a disjointed entry process and in many cases the baton is simply not passed on, which causes increased confusion and ultimately increases the time taken to enter the constraints.
Today the layout is typically begun while the schematics are still being completed. Whether for feasibility studies for placement or for routing, the layout engineer needs the constraints as early as possible. Passing the baton can again impact this parallel activity.
In an attempt to combat this, some companies have developed a process where users export portions of the constraints database, make changes and then merge the changes back together at a later stage. Although this does help, it also has some major disadvantages: Generally, the design has to be packaged before the "copies" can be made. In this environment schematic changes cannot be easily carried out - incomplete data has to be remerged and then split again.
This approach also requires a fair amount of up-front planning with specific milestones having to be reached. The chance that data will be out of step is also extremely high, and shared data are also problematic. This includes any data such as the board stackup, matching rules and net type definitions for trace width and clearances.
These data are used by all the designers equally. If engineers want to use specific net types that do not already exist, they must either merge back to synchronize the data before adding the new net width data, or hope that other engineers do not create the same net data with different values.
This process is difficult enough with two or three designers, but some companies employ many more designers who need to enter constraints into the same design. Coordinating the pseudo-parallel approach discussed here is extremely difficult, and many companies shy away from it.
To drastically reduce the time taken to enter the rules, a paradigm shift is required: The ability to enter constraints concurrently. Allowing each designer to enter his constraints concurrently reduces the total time spent and also allows each user to enter them at the appropriate time.
To be effective, a concurrent constraint entry system has to provide some specific capabilities. Primarily, it must allow users to enter the constraint data concurrently, i.e., all designers should be able to open the constraints system on the same design simultaneously, and store this data in the same database, shown in Figure 2. There should be no need to merge the data at any stage.
Figure 2: Today's large number of nets and high-speed constraints make collaborative, concurrent-entry constraint editors a must for efficient PCB design.
The constraint entry system must also be tightly integrated to the schematic capture and layout applications. Engineers want to be able to enter constraints as they capture their schematic as this follows a natural thought process. To allow this free-flowing constraint entry, the system should allow designers to add components/nets to the schematic and see them in the constraints view dynamically without the need to compile or package the design data first. The designer does not have to complete a successful package step prior to constraint entry. All too often a user may want to simply add some rules to a design, only to find another user is employing a cutting-edge component that is not even in the library yet. By removing this restriction, the constraint entry can continue at the designer's pace.
To effectively collaborate when entering constraints, each designer should be able to dynamically see changes made by other engineers as they happen. This eradicates the problems associated with shared data and data duplication. There must also be a mechanism to temporarily lock the data as it is being edited, and this should also highlight the user who is actually editing the data. The data should remain highlighted to alert other users that this data has already been edited. It is then simply a matter of avoiding this data or contacting the original data author before changes are made.
The front-end engineers and layout designers are collaborating on the design in a parallel processing exercise. During the initial stages of the layout phase when the design is changing rapidly, there is a need to use the latest version of the constraints. The layout engineer should be able to easily and quickly read in any constraint changes from the front-end design without having to perform a full connectivity-based forward annotation which again relies on all the front-end data being 100% correct.
Simple indicators should alert them to new changes being available and, through the constraint system, be able to see what those changes are. The layout engineer can then incrementally load these changes when appropriate.
Constraint entry is a major component of today's design process, and greater consideration must be placed on the entire rules entry task. The entry methods that were used 10 years ago are no longer effective; the introduction of spreadsheet-based systems has greatly improved the situation by allowing the electronic engineers, the true constraint owners, to easily enter the rules themselves.
But even with this automation, the increase in the number of connections and the complexity of the rules, and the diversity of the rule sets has often kept the time spent entering the constraints at the status quo.
True concurrent rules definitions by multiple disciplines will deliver the drastic time reduction needed in the rules entry process.
Andy Critcher is a product architect with Mentor Graphics Corp.