Shrinking Silicon, EMI, and SI

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As IC features continue to shrink, the PCB designer’s job gets more interesting—signal speeds and rise times are increasing, they’re encountering EMI and signal integrity issues once only seen in the RF world.

Dr. Todd Hubing is a longtime EMC instructor, president of LearnEMC, and a professor emeritus of the Electrical and Computer Engineering program at Clemson University. I asked Todd to discuss the challenges that shrinking silicon can present for traditional PCB designers, as well as the opportunities and benefits of smaller chip features.

Andy Shaughnessy: Shrinking silicon is causing an increase in EMI and SI issues for PCB designers and EEs. What sort of problems does shrinking silicon cause?

Todd Hubing: When the features of an IC shrink, transition times tend to be faster, and the high-frequency content of digital signals tends to increase. When newer, faster ICs are used in products that were designed with the older versions of those ICs, those products can suddenly start failing to meet EMC or SI requirements even though there was no nominal change in the design. ICs with smaller features can also be more susceptible to damage by voltage transients, though that largely depends on the mitigation features built into the design.

Shaughnessy: What is the relationship between smaller silicon and EM fields, and what can these designers do to proactively fight EMI and SI?

Hubing: Field coupling directly from an IC is not directly affected by smaller silicon. Field coupling depends more on the currents pulled through the inductance of the lead-frame. Shrinking the features on the silicon can cause those currents to be higher or lower at any given frequency depending on the application.

To protect against future silicon feature-size changes, PCB designers should always proactively control the transition times of any signal that could ultimately be the source of crosstalk or radiated emissions. They shouldn’t rely on “slow” devices to meet EMI and SI requirements.

Shaughnessy: If we add increased rise time and faster signals into this mix, how does material and material selection figure into the equation? Do you think OEMs should select their material, or allow the fab to do so? 

Hubing: I believe laminate selection is strictly an SI issue, and then only for the fastest digital signals. Choosing whether to let the fabricator select the laminate depends on the many factors, but, in my opinion, that decision is unlikely to be impacted by silicon shrinkage. 

To read this entire interview, which appeared in the February 2023 issue of Design007 Magazine, click here.


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