-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
The Test Connection: Spreading the Word About DFT
December 7, 2022 | Andy Shaughnessy, PCB Design007Estimated reading time: 3 minutes
As signal speeds continue to increase and feature sizes decrease, PCB designers are beginning to pay greater attention to test and design for test (DFT) strategies. Bert Horner, president of The Test Connection in Hunt Valley, Maryland, is spearheading this drive to show designers the benefits of a solid DFT plan, as well as the downside of not having a test strategy.
I met with Bert at PCB Carolina, where he was exhibiting and presenting a paper during the conference. We discussed his presentation, as well as why designers need to understand test and DFT issues, and why we need to see the PCB as one small—but very important—part of the entire system.
Andy Shaughnessy: Bert, it’s nice to see you. It’s been a while.
Bert Horner: Thank you for speaking with us today. It’s been a really good show.
Shaughnessy: Yes, it’s packed in here. You just gave a presentation, so why don’t you tell me about your class content and the response you received?
Horner: The Test Connection sees an opportunity to promote test strategy and design for test. As you know, we’re working with I-Connect007, writing a book about testing. I took a subset of that on test strategies for my presentation here today. It whets their taste buds and incorporates a thought pattern on test—starting with the design process. We hope it’s a good starting point for what we will cover in the book on test strategies. Right now, we’re at a point where we can bring that to fruition with some designers. Designers don’t always know what is happening on the back end, so we want to help them get more familiar with test protocols and test solutions and inspection as well.
Shaughnessy: For a lot of designers, test has traditionally been something of an afterthought.
Horner: Yes. We’re trying to encourage the design for test (DFT) with a test strategy that starts as early as the schematic level. We use ASTER TestWay, but Siemens EDA has a similar tool and there is another tool out there as well. Designers are starting to address this. We think they can save money in the long term by spending a little bit of time and money throughout the design process.
Shaughnessy: I heard that one attendee asked a question, and it triggered a long Q&A session.
Horner: Yes, we had a question about in-circuit test and boundary scan being done at the same time, which started a snowball of questions, and it was a lot of exciting conversations. It wasn’t just me and the audience, but audience member to audience member. It’s fun to be involved in those kinds of presentations, and I could see that there was a demand for DFT and test strategies among designers.
Shaughnessy: It sounds like there’s a definite thirst for knowledge about test.
Horner: It’s time, and we’re here to quench that thirst. They’re seeing that DFT can save them time and effort, and the exposure of lost revenue and the fear of being known in the industry for shipping a bad product goes a long way.
Shaughnessy: Right. A lot of people just looked at it as test. It wasn’t seen as a value add because it’s not necessarily making the board “better,” but you’ve got to look at it from a big picture perspective.
Horner: Yes, that’s right. The board is only a component of the whole system, and if you don’t build that component, you run the risk of not having a working unit.
Shaughnessy: How has your year been going at Test Connection?
Horner: For Test Connection, 2022 has been a very good year for us. We continue to see growth. We do see the supply chain challenges, but we’re able to navigate through this and be able to offer a test solution in a timely fashion.
Shaughnessy: Great. Anything else you want to add?
Horner: The economy is always in question, but the industry as a whole is undergoing a bit of a renaissance, as we hope some of the technology comes back to North America. We’re positioned to help support that need.
Shaughnessy: All right. Good talking to you.
Horner: You too, Andy.
Suggested Items
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.