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Electronic designs are increasing in capacity, complexity, and performance. This is coupled with increasing pressure to get new products to market as quickly as possible while, at the same time, ensuring that these products are robust and will not fail in the field. The only practical way to address all these diverse requirements is to make design and verification tools and methodologies more powerful, intuitive, and easier to use.
Almost any electronic development methodology and/or workflow can be segmented into three main stages: a pre-design exploration phase, the design phase itself, and a post-design verification phase (Figure 1).
Figure 1: Electronic development has three main stages: explore, design, and verify.
Historically, the engineers responsible for the exploration, design, and verification stages have used different tools. In this case, the exploration and design teams often prefer to use more simplistic tools that are easier to use. However, these tools then do not correlate 100% with the results from the tools preferred by the verification team which requires more powerful and sophisticated tools to ensure design integrity. What’s more, all the tools in use across these three stages have traditionally been standalone point tools that are not well-integrated into the overall environment, thereby adding unnecessary risk and error into the workflow.
To complicate things further, communication from the verification team back to the design team is often ad-hoc, being composed of screenshots, documents, emails, etc. As a result, a typical development flow tends to involve multiple iterations between the verification team discovering problems and the design team fixing them, hopefully without introducing new issues into the mix.
On top of this, it is also important to note that the “shift left” that’s happening with electronic design means that it is no longer sufficient for signal integrity (SI) and power integrity (PI) analysis to be performed in isolation. For example, accurate SI analysis cannot be performed without considering what’s going to be happening on the power plane, especially in the case of designs featuring low-voltage devices, which makes it essential to accurately model noise and ripple on the power distribution network (PDN).
From an efficiency standpoint, it’s imperative to move as much of the SI/PI analysis upstream as possible, making sure that the design is as SI/PI ready as it can possibly be before handing it off to the signoff verification team.
Bottom line is that customers require a fully integrated, front-to-back constraint-driven SI/PI flow that starts in the exploration phase and drives the process all the way through to final signoff (Figure 2), accelerating turn-around time, minimizing risks, and improving overall product quality.
Figure 2: What is required is a fully integrated constraint-driven SI/PI design flow.
For instance, early “what if” analysis performed upfront in the exploration phase can be used to lay down initial rules and develop first-pass constraints with respect to things like the floorplan, the routing plan, and the PDN. These constraints, which are used to drive the SI and PI tools, can be augmented and evolved as the design progresses and more detailed information becomes available.
In the case of PI, for example, a design engineer working in the exploration phase can start at the bill of materials (BOM) using a power feasibility tool to perform tasks like decoupling capacitor selection and initial PI constraint definition. Similarly, a layout designer can start at the floor planning stage by performing a first-pass PI analysis directly on the layout.
And for the verification team, these members are comfortable using their tools with or without a design environment framework. By comparison, in the case of the exploration and design teams, any verification tools they use must be accessible from within their preferred design tool framework and able to facilitate in-design analysis (IDA).
In order to prevent workflow discontinuities between the exploration, design, and verification stages and teams, the same verification engines should be used throughout. Having said this, the verification tool user interface (UI) presented to the exploration and design teams must be intuitive and easy to use. As part of that, it’s necessary to supply the exploration and design teams with IDA-enabled workflows that provide straightforward execution procedures. Following this workflow guidance means that infrequent users do not need to keep on re-learning UIs and use models. Yet it’s also possible users can natively edit their design to address any discovered SI/PI issues without being obliged to switch back and forth between disparate tools.
Streamlining engineering productivity by adoption of a next-generation IDA-enabled exploration, design, and verification workflow delivers a win-win-win for all involved. Detecting and fixing problems early in the development flow can dramatically reduce the number of pre-signoff iterations, thereby making the entire development flow more predictable, preventing manufacturing partners and component suppliers having to wait for signoff to occur, all the while getting robust, risk-free products to the market faster.
Brad Griffin is a product management group director for the Multiphysics System Analysis Group at Cadence Design Systems, Inc., and the author of The System Designer’s Guide to… System Analysis (a free eBook available for download).