Zuken Joins UCLA CHIPS Consortium

Reading time ( words)

Zuken has joined the UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), a collaborative academic / industry research endeavor, to develop solutions to address the challenges associated with the growing demand for computing power in heterogeneous computing environments.

UCLA CHIPS consortium consists of industrial partners from material suppliers, equipment manufacturers, foundries to system integrators, and includes support from universities and government agencies and industrial consortia, working collaboratively to develop new packaging technologies and system architectures and develop the next generation workforce.

Zuken’s role in the consortium is to enable the team at UCLA CHIPS to utilize the system-level design capabilities of CR-8000 to layout and optimize interconnect structures between bare dies on the substrate level, along with using CR-8000 Design Force as part of the engineering curriculum to educate students in learning how to design and solve high-speed issues.

“Classical CMOS scaling has achieved an 3000X reduction in feature size over the last several decades,” explains Profesor Subramanian S. Iyer, Distinguished Professor at the UCLA Electrical and Computer Engineering and director of UCLA CHIPS. “Although it is still continuing, development and manufacturing costs are rising dramatically. At the same time, other aspects of the system such as the package and board miniaturization have not kept up, while the required effort for integrating more and increasingly diverse functions in a SOC approach is growing exponentially.” UCLA CHIPS is, therefore, looking beyond SOC integration at the system level: “At CHIPS we are focused on packaging and system level integration schemes to improve the overall system performance rather than improving the individually packaged components,” says Iyer.

Introducing a Moore’s Law for Packaging

UCLA CHIPS has pioneered the concept of small dielet integration directly on a Silicon-based interconnect fabric (Si IF) or a flexible Fan-out wafer-level Package (FlexTrate). This allows for extremely tight integration of heterogeneous dies leading to a heterogeneous System on Wafer. This also permits us to scale the package significantly—a veritable Moore’s Law for packaging. Inter-die connections may be scaled from BGA pitches of several hundred microns to a few microns and inter-die spacing may be reduced down to 20 mm. This allows for significant improvements in latency, bandwidth and energy per bit over conventional packages.

Through its ability to model and layout complex designs on a system level in 2D and 3D, Zuken’s CR-8000 electronic design environment is ideally suited to model the complex die stack-ups and interposer designs required by the Silicon Interconnect Fabric and FlexTrate paradigms. As part of its corporate commitment to engage with customers in the investigation of new solution approaches, Zuken is providing design tools and services both for the CHIPS initiative and for electrical engineering course work in the UCLA curriculum.

Targeted Solutions For Today’s Complex Product Development Requirements

Humair Mandavia, Chief Strategy Officer and head of Zuken’s SOZO Center in San Jose, California, says, “Our R&D team in San Jose has been established to collaborate more closely with our customers and partners in Silicon Valley and across the US to help identify new technologies and methodologies for hardware design. Our partnership with UCLA CHIPS is another example of this approach that is fruitful for both Zuken and our customers: It puts us into an ideal position to provide more timely and targeted solutions for today’s increasingly complex product development requirements.”



Suggested Items

‘The Trouble with Tribbles’

06/17/2021 | Dana Korf, Korf Consultancy
The original Star Trek series came into my life in 1966 as I was entering sixth grade. I was fascinated by the technology being used, such as communicators and phasers, and the crazy assortment of humans and aliens in each episode. My favorite episode is “The Trouble with Tribbles,” an episode combining cute Tribbles, science, and good/bad guys—sprinkled with sarcastic humor.

IPC-2581 Revision C: Complete Build Intent for Rigid-Flex

04/30/2021 | Ed Acheson, Cadence Design Systems
With the current design transfer formats, rigid-flex designers face a hand-off conundrum. You know the situation: My rigid-flex design is done so now it is time to get this built and into the product. Reviewing the documentation reveals that there are tables to define the different stackup definitions used in the design. The cross-references for the different zones to areas of the design are all there, I think. The last time a zone definition was missed, we caused a costly mistake.

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.

Copyright © 2021 I-Connect007. All rights reserved.