Cadence to Showcase Signal and Power Integrity Solutions at DesignCon 2018


Reading time ( words)

Cadence Design Systems, Inc. will showcase its latest Sigrity signal and power integrity technologies, high-speed DDR-4400 IP integration and advanced packaging solutions during this year's DesignCon in booth 711, from January 30 to February 1, 2018, in Santa Clara, California.

Cadence experts are scheduled to discuss new developments in these technologies and how they can help solve today’s signal integrity challenges during the following speaking sessions:

  • Panel—Machine Learning Advances in Electronic Design: Tuesday, January 30, 4:45 p.m. – 6:00 p.m., David White, senior director of R&D, Cadence; Christopher Cheng, distinguished technologist, Hewlett-Packard Enterprise; Paul Franzon, Cirrus Logic distinguished professor, North Carolina State University; Madhavan Swaminathan, John Pippin Chair professor, Georgia Institute of Technology
  • Reduction of Mode Conversion in SerDes Links: Wednesday, January 31, 8:00 a.m. – 8:45 a.m., Mehdi Mechaik, staff application engineer, Cadence
  • Temperature- and Geometry-Dependent Analysis of High-Speed PCB Traces: Wednesday, January 31, 8:00 a.m. – 8:45 a.m. and February 1, 8:30 a.m. – 9:10 a.m., An-Yu Kuo, senior group director, and Jian Liu, SI engineer, Cadence; Soumya De, SI engineer, Han Gao, SI engineer, Yaochao Yang, principal engineer, Miroslav Grubic, SI engineer, Cisco Systems
  • Panel—The Impact of Machine Learning on Solution Space Analysis: Are Circuit and Channel Simulation Obsolete? Wednesday, January 31, 1:00 p.m. – 2:00 p.m., Ken Willis, product engineering architect, and Kumar Keshavan, senior software architect, Cadence; Chris Cheng, distinguished technologist, Hewlett-Packard Enterprise; Madhavan Swaminathan, John Pippin Chair professor, Georgia Institute of Technology; Dale Becker, chief engineer of electronic packaging integration, IBM; Ken Wu, staff hardware engineer and signal/power integrity manager, Google
  • Panel—IBIS-AMI: New Users, New Uses: Wednesday, January 31, 3:45 p.m. – 5:00 p.m., Donald Telian, SI consultant, SiGuys; Steven Parker, principal member of technical staff, GLOBALFOUNDRIES; Todd Westerhoff, VP, semiconductor relations, SiSoft; Stephen Scearce, hardware engineering manager, Cisco Systems; Ken Willis, product engineering architect, Cadence; Michael Mirmak, senior SI technical lead, Intel
  • Performance Analysis for Next-Generation PCIe Interface: Thursday, February 1, 9:00 a.m. – 9:45 a.m., Mehdi Mechaik, staff application engineer, and Blake Bader, application engineering director, Cadence
  • DDR-4400 IP Model Development Using AMI Builder: Thursday, February 1, 9:20 a.m. – 10:00 a.m., Chung Huang, design engineering director, and Zhen Mu, product engineering architect, Cadence
  • Backchannel Modeling and Simulation Using Recent Enhancements to the IBIS Standard: Thursday, February 1, 10:00 a.m. – 10:45 a.m., Ken Willis, product engineering architect, Kumar Keshavan, senior software architect, and Ambrish Varma, senior principal software engineer, Cadence
  • Advanced IC Packaging Trends and Their Impact on EDA Tools: Thursday, February 1, 10:15 a.m. – 10:55 a.m., John Park, product management director, Cadence
  • IBIS-AMI for PCI Express Gen 4: February 1, 11:00 a.m. – 11:45 a.m., Greg Edlund, senior engineer, IBM; Mehdi Mechaik staff application engineer, Ken Willis, product engineering architect, Ambrish Varma, senior principal software engineer, and Kumar Keshavan, senior software architect, Cadence
  • HSSO—Physical Structure Optimization for High-Speed Interconnects: Thursday, February 1, 11:05 a.m. – 11:45 a.m., Jack Stone, senior signal and power integrity engineer, Intel
  • Brand-New Electrical and Thermal Co-Simulation Analysis: Thursday, February 1, 2:00 p.m. – 2:40 p.m., Abby Wei-Chien Chou, senior engineer, Daniel Ying-Tso Lai, senior deputy manager, and Gino Chun-Jen Chen, senior deputy manager, Foxconn
  • A New Platform Power Integrity Design Approach with SPIM and UPIT: Thursday, February 1, 2:50 p.m. – 3:30 p.m., Xingjian Kinger Cai, engineering manager, Dennis Chen, platform application engineer, Jimmy Hsiao, hardware power customer engineer, Chi-te Chen, staff power integrity engineer, Yun Ling, sr. principal engineer, and Steven Yun Ji, sr. engineering manager, Intel
  • Panel—Temperature and Bias-Dependent Passive Component Models: Thursday, February 1, 3:45 p.m. – 5:00 p.m., Bradley Brim, senior staff product engineer, Cadence; Istvan Novak, senior engineer, Oracle; Shoji Tsubota, engineering manager, Murata
  • DDR5 Modeling Using Automated IBIS-AMI Modeling Technology: Thursday, February 1, 3:45 p.m. – 4:25 p.m., Randy Wolff, principal engineer, Micron Technology

The following demonstrations are scheduled for the show:

  • Constraint-driven power integrity design and analysis, featuring easy setup with automated model and source/sink assignments
  • Using patented simulation techniques to analyze equalization associated with high-speed DDR memory interfaces
  • Multi-gigabit serial link design and analysis featuring compliance testing for popular interfaces such as PCI Express® (PCIe®) 4.0
  • DDR-4400 IBIS-AMI model development
  • Streamlining the flow between IC design and package/PCB design

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at cadence.com.

Share

Print


Suggested Items

IPC Reliability Forum Wrap-up With Brook Sandy-Smith

08/12/2019 | Andy Shaughnessy, Design007 Magazine
I attended the recent IPC High-Reliability Forum and Microvia Summit in Baltimore, Maryland. The speakers and panelists focused on a variety of topics, but one issue that kept popping up was the failure of some microvias on military and aerospace PCBs. Fortunately, some smart technologists are focusing on determining the cause of these via failures. I asked Brook Sandy-Smith, IPC’s technical education program manager, to give us a quick wrap-up of this event.

Denny Fritz: The Difference Between Quality and Reliability

08/06/2019 | Andy Shaughnessy, Design007 Magazine
I recently spoke with industry veteran (and I-Connect007 columnist) Denny Fritz about the relationship between quality and reliability—two terms that are unequal but often used interchangeably. We also discuss the current state of lead-free solders in the U.S. military and defense market as well as the microvia reliability issues Denny focused on at IPC’s High-Reliability Forum and Microvia Summit in Baltimore, Maryland.

26 Meters of Flex!

07/25/2019 | I-Connect007 Editorial Team
Barry Matties spoke with Philip Johnston, managing director of Trackwise Designs, about the company’s patented length-unlimited multilayer printed circuits aimed at replacing conventional wire harnesses. Originally created for the aerospace industry, Trackwise has since seen growing interest from a number of different industries. Jake Kelly, managing director and chairman of Viking Test Ltd., also joined the conversation to discuss the importance of having a flexible equipment supplier when dealing with such a unique technology.



Copyright © 2019 I-Connect007. All rights reserved.