SiSoft Preparing for DDR5 Simulation Next Year

Reading time ( words)

DDR5 is expected to double the memory bandwidth and density of DDR4. I recently spoke with SiSoft CTO Walter Katz about his company’s efforts to hit the market with this game-changing technology in 2018.

ANDY SHAUGHNESSY: I understand SiSoft is preparing for the upcoming DDR5 standard. What does this mean for the user?

WALTER KATZ: DDR5 is expected to range from 3,200 million transfers/second (MT/s) to 6,400 MT/s. These high data rates, when combined with the discontinuities inherent in DDR5 system topologies, will cause significant Inter Symbol Interference (ISI). This ISI will require that active equalization techniques be used in both the controller and memory I/O buffers to recover a usable signal, similar to what we have seen in serial channels for some time now. JEDEC is setting the standard for the equalization used in the memory chips, while equalization methods for the controller will be determined independently by each controller manufacturer. So let’s focus on the memory devices. Currently, there is no requirement for equalization on the memory’s driver (the memory read operation), while we expect to see a requirement for a four-tap decision feedback equalization (DFE) on the memory’s receiver for both DQ write and address/command operations. A four-tap DFE adds (or subtracts) a voltage to the voltage at the receiver pad based on the values of the previous four symbols (bits) that have been received. There is also some consideration of including a peaking filter before the DFE in the memory’s receiver; we’ll have to wait and see how that plays out.

SHAUGHNESSY: We’re hearing about AMI models being used to model DDR5 data transfers. Can you give a brief summary of how an AMI works?

KATZ: The IBIS-AMI, or AMI (Algorithmic Modeling Interface) was created in 2007 to help analyze high-speed SerDes (serialize/deserialize) channels. Today, those channels operate between 3 Gbps and 56 Gbps, and IBIS-AMI has been used to create hundreds of IBIS-AMI models for systems designers to use with their design simulations. At these frequencies, both ISI and loss are significant impairments, and the energy from a specific transition can affect the signal at the receiver from before the main body of signal itself arrives and for many unit intervals (UI) afterwards. Millions of bits need to be simulated to properly evaluate channel behavior, which is why IBIS-AMI has supplanted traditional SPICE methods for serial link analysis. AMI assumes that the I/O buffer analog models are linear and time invariant (LTI). The interconnect between the buffers is also LTI, which means the combination of the analog I/O and channel can be characterized using circuit simulation techniques and then combined with equalization models to predict the overall link behavior. The AMI models describe transmit (Tx)/receive (Rx) equalization behavior and are supplied as executable models in the form of dynamically linked libraries (DLL in Windows, shared objects in Linux) that are linked directly into EDA simulators at simulation runtime. The IBIS Open Forum is the industry organization responsible for the management of the IBIS-AMI specification. These executable models therefore model the detailed equalization behaviors of both the transmitter and receiver, while protecting the device manufacturer’s IP because they are supplied as executable code. AMI models can be used to do two different types of simulations: statistical and time domain. Statistical simulations can predict the performance of simulations for essentially all possible patterns. Time domain simulations can more accurately handle non-linear and adaptive behavior in the buffers, but are typically limited to simulations that are 10 million UI long.

SHAUGHNESSY: How would AMI models be used to model DDR5 topologies?

KATZ: Serial channels are differential, point to point topologies with the clock embedded as part of the signal, while DDR5 channels are single ended, multi-drop topologies that use separate signals for data and the strobe (clock) signal used to sample the data. So, while we can apply AMI techniques to DDR5 analysis, we need to pay careful attention to the differences between the original applications of AMI modeling and how we apply those techniques to DDR5 applications. In its simplest form, we could approach DDR5 modeling with AMI the same way we approach serial channel modeling: characterize the analog channel, derive an impulse response and then process it with the algorithmic models to determine the effects of equalization. We simulate the analog channel in SPICE with a small rise time step to extract a step response with adequate resolution, then differentiate that to create the impulse response we need for algorithmic processing.

To read this entire interview, which appeared in the October 2017 issue of The PCB Design Magazine, click here.


Suggested Items

Advanced Stackup Planning with Impedance, Delay and Loss Validation

08/02/2018 | Yuriy Shlepnev, Simberian
A typical PCB design usually starts with the material selection and stackup definition—the stackup planning or design exploration stage. How reliable are the data provided by the material vendors and PCB manufacturers? Can we use these data to predict trace width and spacing for the target trace impedance or to calculate delays or evaluate the loss budget?

Achieving Optimum Signal Integrity During Layer Transition on High-Speed PCBs

07/11/2018 | Chang Fei Yee, Keysight Technologies
In electronic systems, signal transmission exists in a closed-loop form. The forward current propagates from transmitter to receiver through the signal trace. Meanwhile, the return current travels backward from receiver to transmitter through the power or ground plane directly underneath the signal trace that serves as the reference or return path. The path of forward current and return current forms a loop inductance. It is important to route the high-speed signal on a continuous reference plane so that the return current can propagate on the desired path beneath the signal trace.

Faster Board Speeds Demand Constraint-Driven Design

06/19/2018 | Ralf Bruening, Zuken
Using powerful constraint techniques can be a double-edged sword. While the design process is made much safer by including constraints, it is all too easy to over-constrain the design and make it impossible to complete routing and placement. Even paper design guidelines can make products uneconomic to produce unless a great deal of engineering knowledge is applied during the design.

Copyright © 2018 I-Connect007. All rights reserved.