Beyond Design: How to Handle the Dreaded Danglers, Part 2


Reading time ( words)

In Part 1 of this series, I deliberated on how dangling via stubs distort signals passing through an interconnect and also decrease the usable bandwidth of the signal. This is due to the via stub acting as a transmission line antenna, which has a resonant frequency determined by the quarter wavelength of the structure. The conventional solution to this problem is to back-drill (or control depth drill) the vias to bore out the via stub barrels, so that the via stubs are reduced in length if not completely removed. This month I will look into all the possible solutions to alleviate this issue.

 1. Back-drill the stub

Back-drilling is a process to remove the stub portion of a plated through-hole (PTH) via. It is a post-fabrication drilling process where the back-drilled hole is of larger diameter than the original PTH. This technology is often used instead of blind via technology to remove the stubs of connector vias in very thick high-speed backplane designs. State-of-the-art board fabrication shops are able to back-drill to within 8 mils of the signal layer, so there will always be a small stub portion attached to the via.

High-speed, SERDES, serial link-based backplanes generally have thick substrates. This is due to the system architecture and backplane to card interconnect requirements such as press-fit connectors. Back-drilling the via stub is a common practice, on thick PCBs, to minimize stub length for bit-rates greater than 3Gbps (1.5GHz). However, at transmission rates >10Gbps (5GHz), back-drilling alone may not be adequate to reduce jitter and bit error rate (BER).

Figure 1 shows the effects of excessively long via stubs on a high-speed differential pair. On the left, the differential pair is simulated using a pseudo random bit stream (PRBS) with lossy transmission lines enabled; note the open eye pattern. However, on the right, I had included via modelling, which enables the via parasitics and highlights the effects of via resonance. The high-frequency harmonics are attenuated, rolling off the signal rise time, distorting the signal, reducing bandwidth and closing the eye.

Vias can appear as capacitive and/or inductive discontinuities. These parasitics contribute to the degradation of the signal as it passes through the via. At high frequencies and with thick backplane substrates, it is imperative that these issues are addressed.

Back-drilling typically requires specialized equipment, and further requires that the back-drill be precisely located over the vias. As such, the back-drilling process, especially two sided back-drilling, is expensive due to drill breakage and yield issues and is very time-consuming.

To read this entire article, which appeared in the September 2016 issue of The PCB Design Magazine, click here.

Share

Print


Suggested Items

AltiumLive Munich: Day 1 Keynotes

01/28/2019 | Pete Starkey, I-Connect007
The weather forecast was wrong! Despite my apprehension and winter clothes, there was very little snow at the Hilton Munich Airport. It could have been any season of the year inside the splendid convention facility, which was also the venue for the second European AltiumLive design summit. AltiumLive brought together a family of over 220 electronics engineers and designers eager to learn from top industry experts and applications specialists who were equally eager to share their knowledge and experience freely.

Martyn Gaudion on Signal Integrity Modelling and Stackup Tools

12/11/2018 | Pete Starkey, I-Connect007
The accuracy of signal integrity modelling continues to improve, and stackup tools are becoming widely used, which now include material suppliers' datasheet information. During the recent electronica show in Munich, Germany, Martyn Gaudion, managing director at Polar Instruments, explained how Polar often serves as a bridge between PCB design and fabrication, and why educating his customers is so critical.

Lee Ritchey Returns to AltiumLive with 32 Gbps Design Class

09/26/2018 | Andy Shaughnessy, Design007 Magazine
Lee Ritchey was one of the instructors for last year’s inaugural AltiumLive event, which drew hundreds of PCB designers. Now, Lee is back, teaching a high-speed design class at next week’s AltiumLive in San Diego. That class is sold-out, but you can catch Lee teaching the same class at the January AltiumLive event in Germany. I asked Lee to explain what he plans to cover in this course, and why PCB designers and design engineers should consider attending one of the events.



Copyright © 2019 I-Connect007. All rights reserved.