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Mentor Webinar: Ensuring DDR4 Electrical Performance at Intended Data Rates
July 2, 2020 | Mentor, a Siemens businessEstimated reading time: Less than a minute
DDR interfaces have many signal integrity and timing requirements that must be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task, or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates have pushed DDR operating margins to the point where simply following physical design rules is no longer enough to ensure that a design will work as intended.
This on-demand webinar will discuss the different electrical requirements associated with DDR designs and show how board and system designers can use HyperLynx to perform post-route verification themselves, helping free up scarce SI experts to focus on their company’s most challenging analysis problems.
The webinar is presented by Min Maung, a senior technical marketing engineer for HyperLynx Analysis Tools Suite for the Electronic Board Systems segment at Mentor, a Siemens Business.
To view this on-demand webinar, or for more information, click here.
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05/03/2024 | Nolan Johnson, I-Connect007This week’s most important news is strategic—and telling. When one puts together the IPC industry reports, we simply have to include the recent conversation with Shawn DuBravac and Tom Kastner. On the design side, check out the latest “On The Line With…” podcast featuring Brad Griffin from Cadence Design Systems, discussing SI and PI in the realm of intelligent system design.
Synopsys, Samsung Electronics Collaborate to Achieve First Production Tapeout of Flagship Mobile CPU
05/03/2024 | PRNewswireSynopsys, Inc. announced that Samsung Electronics has achieved successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs, with 300MHz higher performance using Synopsys.ai™ full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry's latest Gate-All-Around (GAA) process technologies.
Altair Acquires Research in Flight, Forging a New Path for Aerodynamic Analysis
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Real Time with… IPC APEX EXPO 2024: Software Solutions for Circuit Board Challenges
05/03/2024 | Real Time with...IPC APEX EXPONolan Johnson speaks with Will Webb from Aster Technologies about their software solutions for design teams, manufacturing, test engineers, and process engineers. Aster's software addresses the increasing complexities of circuit boards and the need for alternative testing methods.
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.