02-23-2023

The propagation of electromagnetic energy can be controlled in a number of ways depending on the medium the energy is traveling in. However, electromagnetic waves do not require a medium to propagate. This means that electromagnetic waves can travel not only through liquids, solids, and air, but also through the vacuum of space. What’s more, they do not require electron current flow for the transfer of energy.

02-02-2023

An eye diagram is a useful tool for the analysis of signals used in digital transmission. It provides a quick scan of system performance and can offer insight into the nature of channel imperfections. An eye diagram is simply a graphical display of a serial data signal with respect to time that shows a pattern that resembles an eye. Careful scrutiny of this visual display can give one a first-order approximation of signal-to-noise, clock timing jitter, reflections and skew. In this month’s column, I will take an eyeball look at the eye diagram.

12-01-2022

Ralph Morrison was a physicist who promoted the belief that electromagnetic energy flows in spaces, not the traces. That energy does not flow in the copper traces of a PCB, but rather the energy follows the traces acting as a waveguide and propagates through the dielectric material. This explains many electromagnetic (EM) effects such as radiation from outer microstrip layers and from stripline fringing fields, how components can be magnetically coupled, and why crosstalk is created by overlapping EM fields. But it also raises a few questions.

10-19-2022

Electromagnetic (EM) energy propagates through the dielectric materials of a multilayer PCB guided by the signal traces between the planes, for inner stripline layers, but it acts slightly differently on the outer microstrip layers. Microstrip layers generally have a solid ground reference plane on one side but allow radiation from the boundless surface into the air. A well-thought-out routing strategy can avoid up to 10 dB of radiation from the substrate. Embedding signals between the planes reduces these emissions, and susceptibility to radiation, as well as providing electrostatic discharge protection. So, not only can one prevent noise from being radiated but also reduce the possibility of being affected by an external source.

09-22-2022

In a previous column, I deliberated on why the 2D field solver is an essential tool for all high-speed PCB designers. But like all tools, one needs to know how best to apply its unique features to enhance your design process. Obviously, calculating transmission line impedance, in its various forms, is the prime function but field solvers can also provide additional information to ensure good design practice way before the layout begins.

08-23-2022

There are numerous ways to improve the PCB design and production processes and thereby reduce costs, from fundamental improvements involving a standard form factor and reducing the board size and complexity to technology choices and simulation to reduce iterations. A good starting point would be the IPC standards which were developed by the electronics industry to enhance manufacturability, testability, and assembly. Anyone new to PCB development should initially begin with these standards and then fine-tune them to capture the essence of their design style.

07-25-2022

A field solver is the engine behind signal and power integrity analysis. You never see it but it performs all the magic of simulation. In its elementary form, the field solver can employ Maxwell’s equations to calculate the parasitic elements of a solution space. This method is referred to as 2D extraction and is used to analyze and synthesize a stackup to achieve a target single-ended or differential impedance. The velocity of propagation can also be extracted to perform signal integrity analysis. A field solver can be used as a stand-alone tool or as part of a simulation environment. In this month’s column, I will take a look at 2D field solvers.

06-14-2022

The most common question I get asked by PCB designers is, "Do you need copper ground pours on digital multilayer PCBs?" The short answer is, "It depends." Unfortunately, the myth of copper pours is fueled by reference designs that seem to persistently use this old RF design technique. Copper pours are sometimes used incorrectly simply to fill in the unused space on a board. However, in some cases ground pours may be an advantage. In this month’s column, I will look at where and where not to use ground pours.

05-31-2022

When a transmission line is perfectly matched to the driver and load, the signals propagating electromagnetic (EM) energy are totally absorbed by the load. This is the perfect scenario that all electronics designers strive for. However, this is rarely the case and reflections do occur whenever the impedance of the transmission line changes along its length. This can be caused by unmatched drivers/loads, layer transitions, different dielectric materials, stubs, vias, connectors and IC packages. By understanding the causes of these reflections and eliminating the source of the mismatch, a design can be engineered to perform reliably.

04-21-2022

PCB designers are continually challenged with demands for reduced product size. However, form factor-driven design pressures have been relieved, in part, by the increased use of high-density interconnects (HDIs), which enable more functionality per unit area than conventional PCBs. Leveraging finer lines, thinner materials, and laser-drilled vias, HDIs have played a crucial role in device miniaturization. However, the traditional PCB subtractive etch processing becomes very difficult for feature sizes below 3 mil trace/space. This forces PCB designs to become more complex as electronics packages shrink—adding extra routing layers, and microvia layers, and increasing the number of lamination cycles required, all of which impact yield, reliability, and thus cost.

03-09-2022

Coupling on a multilayer PCB may be a good or bad thing. On one hand, close coupling of signal traces to reference planes and differential pair signals is the best way to prevent common mode radiation and to mitigate electromagnetic (EM) emission. But on the other hand, close coupling of unrelated signal traces can bring us grief with unintentional crosstalk caused by overlapping EM fields. In this month’s column, I will look at where close coupling should be used and where it should be avoided.

03-08-2022

In 2022, PCB designers are faced with two big challenges: demands for increased performance and a condensed product footprint. So, what’s new? Columnist Barry Olney recalls back some 50-odd years ago the challenges for the electronics professional were much the same. "I had just become comfortable with valves and next we had diodes, transistors, and LEDs." This column chronicles these and other changes.

11-24-2021

The growing popularity of wide bandgap (WBG) semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC) has enabled components to achieve higher operating temperatures and power outputs than silicon-based technology. However, this has not eliminated the need for careful thermal management to evenly distribute the heat generated to avoid the formation of dangerous hot spots and to minimize power losses. The heat generated by integrated circuits poses great challenges, especially given today’s higher speeds, smaller board surface areas, and multiple devices populated on PCBs.

10-28-2021

Most electronic products today are assembled using the no-clean soldering process. The need for no-clean solder pastes emerged in response to legislation against the use of ozone-depleting chemicals, and the appeal of removing the costly flux cleaning operations in the assembly of PCBs.

09-23-2021

Power Distribution Network (PDN) planning is a relatively new technology that has become an essential, interrelated component of signal integrity analysis. However, mainstream PCB developers have yet to adopt PDN analysis as a common design process.

08-26-2021

The role of fly-over cables is to isolate signals from the limitations of the PCB materials. As signal speeds increase, the dielectric material’s Df and Dk become an issue, and traces need to be shaped and routed perfectly, without skew, to avoid signal coupling, crosstalk, and electromagnetic compliance (EMC) issues.

07-20-2021

A switchback is a 180° bend in a road, rail or path, especially one leading up the side of a mountain. Switchback also refers to a long trombone bend in a tuned serpentine trace. But, rather than increase the delay, of the signal, the switchback actually speeds it up due to the near (NEXT) and far-end (FEXT) crosstalk effects. In this month’s column, Barry Olney looks at why long, parallel switchbacks should be avoided.

06-10-2021

Serial communication has been used long before computers ever existed. The telegraph system using Morse code is one of the first digital modes of communication. All you need is two connections, which makes it simple and relatively robust. Columnist Barry Olney explains how this relates to PCB design.

03-25-2021

Today’s high-speed multilayer PCBs have multiple planes. The ground planes are used for shielding and to provide return current continuity. Whereas, closely coupled power/ground plane pairs provide low inductance power to the ICs and reduce the AC impedance and plane resonance of the Power Distribution Network (PDN).

02-16-2021

Crosstalk is three dimensional and is dependent on the signal trace separation, the trace to plane(s) separation, parallel segment length, the transmission line load, and the technology employed. But, crosstalk also varies depending on the physical stackup configuration. In this month’s column, Barry Olney delves into the properties of microstrip and stripline crosstalk and how to mitigate the concern.

02-01-2021

Stackup planning involves careful selection of materials and transmission line parameters to avoid impedance discontinuities, signal coupling, unintentional return paths, high AC impedance and excessive electromagnetic emissions. Materials used for the fabrication of multilayer PCBs, absorb high frequencies and reduce edge rates thus putting the materials selection process under tighter scrutiny. Ensuring that your board’s stackup and impedances are correctly configured is a good basis for stable product performance.

12-18-2020

The majority of high-speed digital designs take at least two iterations to develop into a working product. However, multilayer boards can be designed to work right the first time with little additional effort. Barry Olney explains how design re-spins will continue to happen until designers make regular use of simulation software.

11-12-2020

As the typical PCB design becomes more complex, so do the techniques and strategies required—not only to complete the design but also to create a functioning product that performs to specification. Barry Olney describes why PCB designers need to understand the underlying high-speed issues of the design based on simulation and then translate these into corresponding design constraints.

10-23-2020

Electromagnetic energy is all around us. Barry Olney looks at how electromagnetic radiation can be emitted from the edges of planes in multilayer PCBs by the fringing fields possibly causing EMC issues.

09-15-2020

Interconnect impedance is a trade-off between the variables, including trace width, trace (copper) thickness, dielectric thickness, and dielectric constant. Barry Olney continues with Part 6 of his stackup impedance planning series and looks at the correct process, as well as the consequences of bad decisions.

08-24-2020

The speed of light is the one universal physical constant that we are yet to break. Barry Olney looks at how to simply measure the speed of light and how the wavelength of electromagnetic energy relates to the multilayer PCB.

08-03-2020

The three most common termination strategies are series, end, and differential. In this column, Barry Olney elaborates on two particular cases of series termination that every PCB designer will come across.

07-15-2020

A high-speed digital signal crossing a split in the reference plane impacts at least three aspects of design integrity: signal quality, crosstalk, and EMI. Barry Olney reviews the two common solutions, plus introduce a third optimal solution for high-speed design.

06-15-2020

The term bandwidth was first used years ago in the RF world to represent the range of frequencies in a signal. In digital electronics, we also use the term to describe the signal spectrum since square waves are made up of numerous sine waves (harmonics) of the fundamental frequency. Barry Olney looks at the relationship between signal rise time and the bandwidth of a digital signal.

06-05-2020

To control the impedance of high-speed signal interconnects, one first needs to predict the impedance of a specific multilayer stackup configuration. Barry Olney describes how a precision field solver is arguably the most accurate way to calculate the single-ended, edge-coupled, and broadside-coupled differential impedance.

04-23-2020

Whenever a signal meets an impedance variation along a transmission line, there will be a reflection, which can seriously impact signal integrity. By understanding the causes of these reflections and eliminating the source of the mismatch, a design can be engineered with reliable performance. Barry Olney looks at how to effectively terminate transmission lines.

10-16-2019

Believe it or not, this is my 100th “Beyond Design” column. To wrap it up, I look back over the past 99 columns and reflect on what I believe to be the most enlightening for high-speed PCB designers, counting down in reverse order of preference.

09-25-2019

Electric fields and magnetic fields play an equal role in moving energy in a multilayer PCB. EM fields also move energy in free space, but not at DC. The presence of voltage implies that there is an electric field, and the changing of that electric field creates a magnetic field. What may not be appreciated is that moving a voltage between two components requires moving energy (not a signal), which requires the existence of both electric and magnetic fields.

08-14-2019

In my previous column series on stackup planning, I described the traditional stackup structures that use a combination of signal and power/ground planes. But to achieve the next level in stackup design, one needs to not only consider the placement of signal and plane layers in the stackup, but also visualize the electromagnetic fields that propagate the signals through the substrate.

07-22-2019

With today’s rapid product development cycles and time-to-market pressures, PCB designers are pushed to their limit. This situation leaves many developers with the question of how to ensure that their high-speed digital design performs to expectations, is stable given all possible diverse environments, and is reliable over the products projected life cycle. As developers avoid the expense and delays of re-engineering the product, they look to employ design integrity methodologies during the design phase.

06-10-2019

Digital design has entered a new realm. Modern high-speed design (HSD) not only requires the designer to continuously break new ground on a technical level but also requires the designer to account for significantly more variables associated with higher frequencies, faster transition times, and higher bandwidths. Ignoring signal and power integrity and electromagnetic compatibility invites schedule delays and increases development costs and the possibility of never succeeding to build a functional product, which is a career-limiting strategy.

05-22-2019

The ability to simulate complex PCB design has become a critical factor in the success of a project. Today’s high-speed processors and SERDES interfaces coupled with sometimes unrealistic time-to-market requirements are pushing design teams toward more nimble development processes. However, there is no point in completing a design on time if it does not work!

04-29-2019

Skin effect and the proximity effect are manifestations of the same principle—magnetic lines of flux cannot penetrate a good conductor. The difference between them is that skin effect is a reaction to the magnetic fields generated by current flowing within a conductor, while proximity effect is generated by current flowing in other nearby traces or planes. The frequency at which both effects begin to occur is the same. In this month’s column, I will focus on the proximity effect.

03-25-2019

PCB substrates are all around us in every gadget we use. The substrate may be rigid or flexible, or a combination of both. It is a carrier for the electronic devices and the signal and power interconnects and is usually planar in structure with conductors separated by insulating dielectric materials. However, each product has a specific performance requirement and may need a distinct type of substrate to comply with the product’s specifications.

02-14-2019

The final part of the 10 fundamental rules of high-speed PCB design focuses on board-level simulation encompassing signal integrity, crosstalk, and electromagnetic compliancy. Typically, a high-speed digital design takes three iterations to develop a working product. However, today, the product life cycle is very short, and therefore, time to market is of the essence. The cost per iteration should not only include engineering time but also consider the cost of delaying the products market launch.

01-02-2019

Part 4 of the 10 fundamental rules of high-speed PCB design deals with the routing of critical signals and return path discontinuities. Needless to say, matched delay and length, differential pairs, and other critical signals should be routed first with the precision they require before less important low-speed and static signals are completed. Maintaining this priority is imperative.

12-13-2018

Planes are essential in today’s high-speed multilayer PCBs. Unfortunately, the number of power supplies required is increasing dramatically with IC complexity. Now, accounting for them all has become a real challenge. The high number of supplies generally leads to higher layer count substrates. In the past, we used to have more signal routing layers than planes; the opposite is now the case when the majority of stackup layers are reserved for power distribution. Although this increases the cost, it may be a godsend because it provides segregation of critical signals to avoid crosstalk and reduces radiation.

11-15-2018

In last month’s column, I introduced the 10 fundamental rules of high-speed PCB design. The first rule was to establish design constraints before commencing the design. This prime strategy sets constraints upfront based on pre-layout analyses or recommendations and guidelines and is integral to the design flow to maintain the established requirements. This month, I will elaborate on the importance of controlling the impedance and floor planning the placement based on connectivity.

09-10-2018

Years ago, when clock frequencies were low and signal rise times were slow, selecting a dielectric material for your PCB was not difficult; we all just used FR-4. And we didn’t really care about the properties of the materials. However, with today’s multi-gigabit designs and their extremely fast rise times and tight margins, precise material selection is crucial to the performance of the product. Materials used for the fabrication of the multilayer PCB absorb high frequencies and reduce edge rates, and that loss in the transmission lines is a major cause of signal integrity issues. But we are not all designing cutting-edge boards and sometimes we tend to over-specify requirements that can lead to inflated production costs.

08-22-2018

What is an acceptable level of crosstalk? That depends on the technology being used, and this level has changed quite dramatically over the years, going from TTL logic devices to today’s high-speed Gbps devices. In this month’s column, I will delve into the threshold of acceptable crosstalk and how to mitigate its impact on high-speed designs.

08-06-2018

Over the years, I have focused on high-speed design, signal and power integrity, and EMC design techniques in a plethora of published technical articles—all of which have key points to consider and present a tremendous amount of information to absorb. In my next few columns, I will elaborate on ten of the most important considerations to embrace to achieve successful high-speed PCB designs that perform reliably to expectations.

07-18-2018

DDR3/4 fly-by topology is similar to daisy chain or multi-drop topology, but it includes very short stubs to each memory device in the chain to reduce the reflections. The advantage of fly-by topology is that it supports higher-frequency operation and improves signal integrity and timing on heavily loaded signals. If you are employing high-frequency DDR4, then the bandwidth of the channel needs to be as high as possible. However, with today’s extremely fast edge rates, the sequencing of the stubs and the end termination, and the associate load, can make a measurable difference in signal quality. In this month’s column I will look at how best to route DDR3/4 fly-by topology.

06-27-2018

Electromagnetic radiation from digital circuits can occur as either differential mode or common mode. Differential mode is typically equal and opposite and therefore any radiating fields will cancel. Conversely, common-mode radiation from two coupled conductors is identical. It does not cancel, but rather reinforces.

05-30-2018

There is an old saying, “You get what you pay for.” Does this mean that you should not expect too much from free software? After all, free software usually comes at a price: the results might be inaccurate, the software might be time-consuming to set up and use, and the tool might overlook issues that require a revision to mitigate. But HyperLynx DRC is the exception to the rule.

04-27-2018

Positioned at our usual table at the local pub in Melbourne, Australia one night in 1972, the boys and I laughed as a school boy, guitarist Angus Young, set up equipment and tuned a guitar. We assumed he was one of the roadies, and were gobsmacked when AC/DC unexpectedly fired up. This month, I will discuss AC coupling (or is it DC blocking?) of high-speed serial links as my taste in music has matured over the years.

03-13-2018

Before you worry (or not) about post-layout PDN DC drop analysis, you first need to design an effective PDN pre-layout. Smart designers prevent problems before they arise, while others waste time and resources trying to fix the mess that they inadvertently created due to their lack of due diligence. Engineers and PCB designers need to visualize and understand how and where the currents flow.

12-06-2017

At low frequencies, traces and components on a PCB behave simply as lossless lumped elements—as taught in Circuit Theory 101. But as the frequency increases, the copper trace and adjacent dielectric(s) become a transmission line, the skin effect forces current into the outer regions of the conductor and frequency dependant losses impact on the quality of the signal. The PCB trace now behaves as a distributed system with parasitic inductance and capacitance characterized by delay and scattered reflections. The behavior we are now concerned about occurs in the frequency domain rather than the familiar time domain. This is the real world of high-speed design.

10-31-2017

Plane pairs in multilayer PCBs are essentially unterminated transmission lines—just not the usual traces or cables we may be accustomed to. They also provide a very low-impedance path, which means that they can present logic devices with a stable reference voltage at high frequencies. But as with signal traces, if the transmission line is mismatched or unterminated, there will be standing waves: ringing. The bigger the mismatch, the bigger the standing waves and the more the impedance will be location dependent.

09-12-2017

As IC die sizes continue to compact due to demand for smaller and faster technology, and as switching speeds continue to improve, rise and fall times are creeping down into the sub-nanosecond realm, a territory previously reserved for microwave engineers. It is a common quandary that established products that have worked flawlessly for years suddenly stop performing reliably, due to a new batch of ICs that is used in the latest production run.

08-23-2017

In an ideal world, the entire signal waveform would uniformly decrease in amplitude, over distance, and the rise time would remain constant. This reduction in amplitude could easily be compensated for by applying gain (cranking up the volume) at the receiver. However, as signals propagate along a lossy transmission line, the amplitude of the high-frequency components is reduced, in magnitude, whereas the low-frequency components are unaffected. This selective attenuation of high-frequency components is the root cause of ISI and collapse of the signal eye.

07-26-2017

The primary issue is generating optimal FPGA pin assignments that do not add vias and signal layers to a PCB stackup or increase the time required to integrate the FPGA with the PCB. Engineers generally do not consider FPGA pin assignments that expedite the PCB layout. Hundreds of logical signals need to be mapped to the physical pin-out of the device, and they must also harmonize with the routing requirements whilst maintaining the electrical integrity of the design.

06-21-2017

I guess we all think of a copper plane as a thick, solid plate of copper that can basically handle any amount of current we sink into it. It also serves to make the circuit layout easier, allowing the PCB designer to ground anything, anywhere without having to run multiple tracks. That may well be the case with DC or very low-frequency analog circuits, but certainly not in the case of high-speed design.

05-29-2017

PCB designers generally take great care to ensure that critical signals are routed exactly to length from the driver to the receiving device pins, but take little care of the return current path of the signal. Current flow is a “round trip” and the critical issue is delay, not length. If it takes one signal longer for the return current to get back to the driver—around a gap in the plane for instance—then there will be skew between the critical timing signals. Return path discontinuities (RPDs) can create large loop areas that increase series inductance, degrade signal integrity and increase crosstalk and electromagnetic radiation.

04-26-2017

The classic coplanar waveguide (CPW) is formed by a microstrip conductor strip separated from a pair of ground planes pours, all on the same layer, affixed to a dielectric medium. In the ideal case, the thickness of the dielectric is infinite. But in practice, it is thick enough so that electromagnetic fields die out before they get out of the substrate. CPWs have been used for many years in RF and microwave design as they reduce radiation loss, at extremely high frequencies, compared to traditional microstrip. And now, as edge rates continue to rise, they are coming back into vogue. This month, I will look at how conformal field theory can be used to model the electromagnetic effects of microstrip coplanar waveguides.

04-03-2017

I originally came up with the concept of an online impedance calculator way back in 1994 when I was working on the PCB layout and design for a new generation of SPARC 20 servers. We basically reformatted a Sun SPARC 20 pizza box motherboard to fit into a 5.25-inch drive slot.

02-24-2017

The impact of lower core voltages and faster edge rates has pushed the frequency content of typical digital signals into the gigahertz range. Consequently, the performance of decoupling capacitors, that are required to complement the power distribution network (PDN) and curb signal induced fluctuations, must also be extended up into this range. However, rudimentary design rules, adequate for frequencies below 100MHz, may not be suitable for today's high-speed digital circuits. The symptoms of an inadequate PDN design are increased power supply noise, crosstalk and electromagnetic radiation leading to poor performance and possibly intermittent operation.

12-21-2016

When common sense fails, tap into your uncommon sense. Basically, common sense teaches us that the way it has always been done is the right way, and that’s just how things are. Following common sense is usually the safe way to go. But the people who are really making a difference in the world are usually the people who try something new. Tapping into our uncommon sense allows us to take a look at things we often take for granted.

11-09-2016

How do we ensure that our high-speed digital design performs to expectations, is stable given all possible diverse environments, and is reliable over the product’s projected life cycle? For the perfect transfer of energy and to benefit from the highest possible bandwidth, the impedance of the driver must match the impedance of the transmission line and be constant along its entire length.

08-17-2016

With the changing demographics, the old-timers in our industry—the master PCB designers—are about to retire and hand over the exacting job of PCB design to the Gen-X and Ys. These generations, shaped by technology, will tackle the most demanding designs without possessing the experience that we veterans benefit from. And to top it off, these up-and-coming designers will be degreed engineers who have to cope with both design and layout tasks as the specialized PCB designer’s positions are phased out.

06-29-2016

There has been a lot of activity in the field of artificial intelligence recently, with such developments as voice recognition, unmanned autonomous vehicles and data mining to list a few. But how could AI possibly influence the PCB design process? This month, Barry Olney will take a look at the endless possibilities.

05-04-2016

Years of experience with one EDA tool obviously develops efficiency, whether the tool be high-end feature-packed or basic entry-level. And one becomes accustomed to the intricacies of all the good and bad features of their PCB design tool. However, there comes a time, with the fast development pace of technology, that one should really consider a change for the better to incorporate the latest methodologies. This month, I will look at productivity issues that impede the PCB design process.

01-04-2016

A high-speed digital power distribution network (PDN) must provide a low inductance, low impedance path between all ICs on the PCB that need to communicate. In order to reduce the inductance, we must also minimize the loop area enclosed by the current flow. Obviously, the most practical way to achieve this is to use power and ground planes in a multilayer stackup. In this two-part column, I will look at the alternatives to planes, why planes are used for high-speed design, and the best combination for your application.

12-15-2015

Ask any group of PCB designers what they think of autorouters and the majority will say that they do not use them because they do not work. I have been battling this mindset for over 20 years now and it still persists today, even with the dramatic advances in routing technology. This way of thinking generally comes from those designers who use the entry-level tools that have limited routing capability. But even the most primitive autorouter may have some useful features. It’s all about changing that mindset of the designer and having a crack at it.

11-16-2015

In the final part of the Stackup Planning series, I will look at 10-plus layer counts. The methodology I have set out in previous columns can be used to construct higher layer-count boards. In general, these boards contain more planes and therefore the issues associated with split power planes can usually be avoided. Also, 10-plus layers require very thin dielectrics, in order to reduce the total board thickness. This naturally provides tight coupling between adjacent signal and plane layers reducing crosstalk and electromagnetic emissions.

09-02-2015

Following on from the first Stackup Planning columns, this month we will look at higher layer-count stackups. The four- and six-layer configurations are not the best choice for high-speed design. In particular, each signal layer should be adjacent to, and closely coupled to, an uninterrupted reference plane, which creates a clear return path and eliminates broadside crosstalk. As the layer count increases, these rules become easier to implement but decisions regarding return current paths become more challenging.

08-12-2015

In Part 1 of the Stackup Planner series, Barry Olney looked at how the stackup is built, the materials used in construction and the lamination process. And he set out some basic rules to follow for high-speed design. It is important keep return paths, crosstalk and EMI in mind during the design process. Part 2 follows on from this with definitions of basic stackups starting with four and six layers. Of course, this methodology can be used for higher layer-count boards—36, 72 layers and beyond.

06-24-2015

The PCB substrate that physically supports the components, links them together via high-speed interconnects and also distributes high-current power to the ICs is the most critical component of the electronics assembly. The PCB is so fundamental that we often forget that it is a component and, like all components, it must be selected based on specifications in order to achieve the best possible performance of the product. Stackup planning involves careful selection of materials and transmission line parameters to avoid impedance discontinuities, unintentional signal coupling and excessive electromagnetic emissions. Barry Olney explains.

06-03-2015

Controlled impedance—it’s all about transmission lines. For perfect transfer of energy, the impedance of the driver must match the transmission line. A good transmission line is one that has constant impedance along the entire length of the line, so that there are no mismatches resulting in reflections. But unfortunately, drivers do not have the exact impedance to match the line (typically 10–35 ohms) so terminations are used to balance the impedance, match the line and minimize reflections.

05-12-2015

Currently, power integrity is just entering the mainstream market phase of the technology adoption life cycle. The early market is dominated by innovators and visionaries who will pay top dollar for new technology, allowing complex and expensive competitive tools to thrive. However, the mainstream market waits for the technology to be proven before jumping in. Power distribution network (PDN) planning was previously overlooked during the design process, but it is now becoming an essential part of PCB design. But what about the learning curve? The mainstream market demands out-of-the-box, ready-to-use tools.

04-08-2015

Creating split planes or isolated islands in the copper planes of multilayer PCBs at first seems like a good idea. Today’s high-speed processors and FPGAs require more than six or seven different high-current power sources. And keeping sensitive analog circuitry isolated from those nasty, fast, digital switching signals seems like a priority in designing a noise-free environment for your product. Or is it?

03-11-2015

At frequencies below 1GHz, the effect of copper surface roughness on dielectric loss is negligible. However, as frequency increases, the skin effect drives the current into the surface of the copper, dramatically increasing loss. When the copper surface is rough, the effective conductor length extends as current follows along the contours of the surface up and down with the topography of the copper surface.

12-03-2014

In Part 1 of his signal integrity series, Columnist Barry Olney examined how advanced IC fabrication techniques have created havoc with signal quality, and radiated emissions. Part 2 covers the effects of crosstalk, timing, and skew on signal quality.

10-22-2014

As system performance increases, the PCB designer’s challenges become more complex. The impact of lower core voltages, high frequencies, and faster edge rates has forced us into the high-speed digital domain. But in reality, these issues can be overcome by experience and good design techniques. If you don’t currently have the experience, then listen-up.

08-27-2014

In his latest column, Barry Olney looks at what types of materials are commonly used for digital design, and how to select an adequate material to minimize costs. He advises, "Of course, selecting the best possible material will not hurt, but it may blow out the costs."

07-30-2014

Concurrent design is the practice of developing products in which the different stages run simultaneously rather than consecutively. It decreases product development time and also time-to-market, leading to improved productivity and reduced costs. The practice is a relatively new process strategy and although the initial implementation can be challenging, the competitive advantage means it is beneficial in the long term.

06-25-2014

PCB surface finishes vary in type, price, availability, shelf life, assembly process, and reliability. While each treatment has its own merits, electroless nickel immersion gold (ENIG) finish has traditionally been the best fine pitch (flat) surface and lead-free option for SMT boards over recent years. But, unfortunately, nickel is a poor conductor with only one third the conductivity of copper.

06-04-2014

Contrary to common belief, the transmission line does not carry the signal itself but rather guides electromagnetic energy from one point to another. It is the movement of the electromagnetic field or energy, not voltage or current that transfers the signal. The voltage and current exist in the conductor, but only as a consequence of the field being present as it moves past.

05-04-2014

One of the greatest myths in PCB design is that we only have to route signal traces from pin-to-pin to make a complete connection. And, that ensuring these traces have matched delay is the only timing issue we need to consider. However, current is not a one way trip--it must complete the circuit back to the source to provide the round-trip current loop.

04-09-2014

In previous columns, Columnist Barry Olney has discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month's column he takes a look at the actual differences between the two.

03-19-2014

In a previous column, Barry Olney discussed various termination strategies and concluded that a series terminator is best for high-speed transmission lines. But, what if there are a number of loads--how should these transmission lines be routed? For perfect transfer of energy and to eliminate reflections, the impedance of the source must equal the impedance of the trace(s) to the load.

02-12-2014

In Part 1 of this column, Barry Olney looked closely at how to choose the right capacitor to lower the AC impedance of the power distribution network (PDN) at a particular frequency. This month he continues from there looking at the one-capacitor-value-per-decade and optimized value approaches.

12-18-2013

While high-speed SERDES serial communications seems to currently be at the cutting edge of technology, maybe it will shortly become an antiquated low-speed solution--even speed-of-light fiber optics may become obsolete. This month, Columnist Barry Olney looks at how quantum physics is transforming our world and how it could affect PCB design.

11-26-2013

The impedance of the trace is extremely important, as any mismatch along the transmission path will result in a reduction in signal quality and possibly the radiation of noise. Mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the load.

11-13-2013

Many challenges face the engineer and PCB designer working with new technologies. For SERDES--high-speed serial links--loss, in the transmission lines, is a major cause of signal integrity issues. Reducing that loss, in its many forms, is not just a matter of reducing jitter, bit error rate (BER) or inter-symbol interference (ISI).

10-16-2013

"If you are a digital designer, you will eventually have SI problems whether you like it or not. But all is not lost. If you learn to work with these issues, then you will soon become proficient with high-speed design," says columnist Barry Olney.

09-18-2013

Design for profit (DFP) is gaining more recognition as it becomes clear that the cost reduction of printed circuit assemblies cannot be controlled by manufacturing engineers alone. The PCB designer now plays a critical role in cost reduction, says columnist Barry Olney.

08-28-2013

Differential skew has become a performance limiting issue for high-speed SERDES links. The operation of such links involves significant amounts of signal processing to recover clocks, reduce the effects of high-frequency losses, reduce inter symbol interference, and improve signal-to-noise ratio.

08-21-2013

No matter what type of memory used in a design, the clock should always have the longest delay. This ensures that the other signals have time to settle before the clock arrives at the device and samples the bus.

07-17-2013

In his last column, Barry Olney discussed how magnetic fields revolve around the earth and how these fields are also present in a multilayer board. Part 2 of "Electromagnetic Fields" will look at how the phenomena influence transmission lines and how they can be applied in a BEM field solver.

06-19-2013

Our whole world literally revolves around electromagnetic fields. Columnist Barry Olney says much insight into high-speed PCB design can be gained by understanding the behavior of transmission lines and the influence of their associated electromagnetic fields.

05-29-2013

Developing the practice of performing a post-mortem analysis on every project facilitates a culture of continuous improvement. This embedded culture of ongoing, positive change is the best way to ensure long-term success according to Barry Olney.

09-19-2012

The key to a successful mixed digital-analog design is functional partitioning, understanding the current return path, routing control and management, and using a common ground plane. Barry Olney takes us into the mix this week.

08-22-2012

Pre-layout simulation allows a designer to identify and eliminate signal integrity, crosstalk and EMC issues early in the design process. This is the most cost-effective way to design a board. Barry Olney explains why in this case, sooner is better than later.

07-18-2012

The power distribution network (PDN) of a multilayer PCB should distribute low noise and stable power to ICs over the entire board area. Ideally, the AC impedance, between power and ground, should be zero, up to the maximum operating frequency for reliable performance.

05-23-2012

Board-level simulation reduces costs by identifying potential problems at the conceptual stage, so that they can easily be avoided, and then catching any further issues during the design process, eliminating the potentially disastrous final-stage changes. By Barry Olney.

05-09-2012

Post-layout simulation covers batch mode simulation, which automatically scans nets on an entire PCB, flagging signal integrity, crosstalk and EMC hot spots. While post-layout simulation can be used for disaster recovery, ideally this process is completed during the design process. Barry Olney explains.

04-04-2012

This month, Barry Olney discusses the traditional serpentine routing for matched length signals and looks at a potentially desirable alternative, the octagonal spiral pattern, that can be especially useful if real estate is at a premium.

12-11-2011

In this column, we will tackle the "microstripum crosstalkus radiarta," an insidious little creature more commonly known as microstrip crosstalk radiation. Thriving on the outer layers of PCBs, crosstalk, like fleas on a dog, can't be eliminated completely or forever; the key is learning how to minimize and control it.

11-03-2011

Is radiation actually attenuated when high-speed signals are routed embedded between the planes? There are specific constraints and factors to consider when assessing just how much attenuation we actually get from embedding the high-speed signals between the planes. Barry Olney breaks it all down.

09-14-2011

By definition, a ground plane in a PCB is a layer of copper that appears to most signals as an infinite ground potential. This month, we discuss best practices for selecting reference planes and routing pairs for high-speed designs on multilayer boards.

08-11-2011

Unintended noise can be a formidable enemy, and it is best to totally eliminate, control or attenuate the emissions at the source. Controlling the impedance of the substrate and terminating the transmission line to match the impedance of the respective source and load significantly reduces radiated noise, virtually eliminating the noise at the source.

07-21-2011

This second and final part in a series examining PCB design techniques will look at a comparison of DDR2 and DDR3, DDR3 design guidelines, pre-layout analysis, critical placement, design rules, and post-layout analysis.