All Systems Go: Auto-Detecting Over- and Under-Derated Parts

Taranjit_Kukal_300.jpgThere are many reasons why a design may fail in the field. How painful would it be if it turned out that a catastrophic failure was caused by a one-cent part, such as an innocuous resistor that was stressed beyond its specified operational parameters? If a product does fail in the field, the costs associated with identifying and remediating the problem can be significant, not least in loss of reputation for the creators and distributors of the device. If only a 1.25-cent resistor had been used in this specific portion of the circuit, thereby saving time, money, resources, and reputation.

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Figure 1: A representative schematic of a small analog portion of a larger circuit.

Every component has a primary attribute that the design engineer is looking for. In the case of resistors and capacitors, for example, their primary attributes are, not surprisingly, their resistance and capacitance values. Components also have secondary aspects that must be taken into account during the design process. For example, a resistor’s maximum power rating needs to be considered. For a capacitor, its maximum voltage rating needs to be taken into account.

Nitin_Bhagwath_300.jpgThese secondary limitations might further be dependent on other factors. Temperature can affect the power rating of resistors, while the type of capacitor (tantalum vs. ceramic vs. electrolytic, etc.) can affect how close to the rated voltage a designer is comfortable with the actual voltage reaching. If the voltage at the capacitor is expected to reach 5V, a designer might not be comfortable with a capacitor rated even for say 6V.

This brings us to the concept of derating. To make sure that the component is not subjected to electrical stresses it wasn’t designed for, its value is “derated.” If a capacitor is expected to handle 5V during operations, a capacitor rated to 12V might be used. Derating a component not only helps to ensure the component isn’t subjected to stresses it can’t handle, but it also helps with the longevity of the components. Components subjected to high electrical stresses—even if those stresses lie within the component’s rated value—can reduce their lifespan.

But there needs to be a balance here. While inadequately derating components can lead to unintended catastrophic issues, over-derating parts can be unnecessarily expensive—especially given the number of small parts in an average board. The trick is to derate each device by the appropriate amount.

Now, you might think that if you are armed with the appropriate specification, it would be easy to apply the appropriate derating factors to each component. Unfortunately, things aren’t so simple. Consider a single resistor connected between the power and ground rails. In this case, we know the voltage of the power supply plus some permitted variation (say ±0.1V), and we know the resistor value plus its tolerance (say 1kΩ ±1%). On the one hand, it’s easy to work out the worst-case current in amps and power in watts. On the other hand, determining whether the wattage selected for the resistor is over-derated or under-derated depends on the operating temperature, and the mathematical relationship between the derating and the operating temperature may be non-trivial. This is just for a single resistor connected between the power and ground rails. In reality, our theoretical resistor would be embedded in a complicated circuit including other components. Determining the voltage and current characteristics of all the components embedded in the heart of such a circuit is much trickier. In turn, this makes the task of determining whether each component is over-derated or under-derated much, much harder.

This sort of analysis requires SPICE-level simulation. Setting up a SPICE simulation for a large number of components can be a time-consuming and daunting task if done manually. That’s not to mention the intimidating fear SPICE strikes into the hearts of many a proud engineer. CAD tools can help here by automating the process of this “electrical stress analysis.” Voltage values are already a part of the schematic data, as are component values. The rest—the current, intermediate voltages, and such—can be calculated by the SPICE simulation. This data can be used to set up and run the simulation “under the hood” without the designer ever having to interact directly with SPICE.

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Figure 2: Presenting the results from an electrical stress test.

The time taken to set up, run, and analyze an analog simulation increases dramatically as a function of the size of the circuit being simulated. CAD tools can again facilitate this situation by partitioning large designs into more manageable chunks and by highlighting mis-derated components (possibly by color coding them to easily identify components that are over-derated or under-derated).

When an under-derated part is found, sometimes the solution is not to replace that part. In many cases, a better strategy is to highlight and review the subcircuit containing that part in question. A part coming under unexpected electrical stresses might be caused by the mis-design of other components. Analyzing the entire sub-circuit can help the designer understand if it’s a question of upgrading a specific part or if the entire subcircuit needs to be redesigned. 

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Figure 3: Identifying the elements forming the subcircuit of which a problematic component is part.

Derating is a critical topic, but it is often managed with a “sledgehammer” solution. Under-derating risks a dramatic product failure, but over-derating leads to lower profit margins for the products. Appropriate derating requires careful analysis of the entire circuit. Using an appropriate CAD tool able to run an electrical stress analysis, this third option can be a practically viable route and a more precise solution.

Nitin Bhagwath is director of product management, PCB front end at Cadence. Taranjit Kukal is senior product engineering architect at Cadence.

Download The System Designer’s Guide to… System Analysis by Brad Griffin along with its companion book The Cadence System Design Solutions Guide. You can also view other titles in our full I-007eBooks library.  

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2022

All Systems Go: Auto-Detecting Over- and Under-Derated Parts

11-17-2022

There are many reasons why a design may fail in the field. How painful would it be if it turned out that a catastrophic failure was caused by a one-cent part, such as an innocuous resistor that was stressed beyond its specified operational parameters? If a product does fail in the field, the costs associated with identifying and remediating the problem can be significant, not least in loss of reputation for the creators and distributors of the device. If only a 1.25-cent resistor had been used in this specific portion of the circuit, thereby saving time, money, resources, and reputation. Taranjit Kukal and Nitin Bhagwath co-host this month's column.

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All Systems Go: Time Traveling to 2030 for ML-Augmented PCB Design

08-23-2022

In our previous column, 'Accelerate Your PCB Designs with Machine Learning,' we explained how artificial intelligence (AI) is an umbrella term embracing technologies that empower machines to simulate human behavior, while machine learning (ML) is a subset of AI that allows machines to automatically learn from past data and events without explicitly being programmed to do so. As ML systems become increasingly complex and capable, the distinction between AI and ML is becoming increasingly blurred.

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All Systems Go: Accelerate Your PCB Designs with Machine Learning

07-06-2022

Even though we hear the terms artificial intelligence (AI) and machine learning (ML) almost daily, there’s still a lot of confusion about the actual meaning of these designations. In a nutshell, AI is an umbrella term embracing technologies that empower machines to simulate human behavior. ML is a subset of AI that allows machines to automatically learn from past data and events without explicitly being programmed to do so. So, how do these play into PCB design?

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All Systems Go: Can You Design Without Electronic Data Management?

06-07-2022

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All Systems Go! Supply Chain Woes—Which Comes First, the Design or the BOM?

04-21-2022

In an ideal world, when developing a printed circuit board (PCB) for an electronic product, decisions made during the design process should drive the bill of materials (BOM). We may think of this as an example of “the dog wagging the tail.” In the real world, however, there has always been some small amount of the BOM driving the design, which we may think of as “the tail wagging the dog.” A classic example of this is when an engineer’s calculations indicate the need for a resistor of 123 kΩ—a 40-cent part—while a 120 kΩ resistor—available for only 4 cents—will provide an almost identical response.

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All Systems Go! Find and Fix Thermal PCB Problems Sooner Than Later

03-17-2022

In an earlier column titled "Bridging the Gap Between Design and Analysis with In-Design Analysis," Brad Griffin discussed how the “shift left” that’s happening with electronic design means it is no longer sufficient for signal integrity (SI) and power integrity (PI) analysis to be performed in isolation. Designing, analyzing and verifying the design in its entirety is key. Another facet of this shift left is the need to address thermal integrity (TI) sooner rather than later. In other words, finding and fixing thermal PCB design issues early in the design process is necessary to save costs, reduce design spins, and maintain your own sanity.

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All Systems Go! Ensuring Power Integrity—Explore, Design, and Verify

02-17-2022

When designing an electronic system, ensuring power integrity (PI) is all about making sure that the power you are putting into the system via the voltage regulator module (VRM) reaches the downstream components in an efficient, sufficient and stable manner. In the not-so-distant past, ensuring the PI of an electronic system was a relatively simple and pain-free task. Many products involved a single PCB populated by readily available off-the-shelf ICs, such as the classic 7400-series devices from Texas Instruments. For the purposes of PI, these ICs, which were presented in low pin count, coarse pin pitch packages could be treated as closed boxes represented by simple power models.

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All Systems Go! Bridging the Gap Between Design and Analysis

01-20-2022

Electronic designs are increasing in capacity, complexity, and performance. This is coupled with increasing pressure to get new products to market as quickly as possible while, at the same time, ensuring that these products are robust and will not fail in the field. The only practical way to address all these diverse requirements is to make design and verification tools and methodologies more powerful, intuitive, and easier to use. In-design analysis provides a way forward.

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All Systems Go! Meet Power Delivery Requirements Upfront with Power-First PCB Implementation

01-06-2022

The drive for faster throughput, increased mobility, and maximum efficiency in modern electronic devices has made power delivery a critical piece of design success. However, meeting the power needs of modern designs is anything but simple. To achieve a robust design, each supply must be capable of delivering sufficient current to every dependent device. In addition, those supplies must be both stable (able to maintain narrow voltage tolerances) and responsive (capable of adapting to transient current demands). Identifying and resolving power delivery problems late in the design process is incredibly difficult. If design power requirements aren’t considered upfront, it can lead to schedule delays and a significant amount of debugging time in the lab. Implementing a power-driven, PCB layout methodology ensures the design process addresses critical power and signal integrity (SI) issues collectively at a time they can be easily solved.

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2021

All Systems Go! Simulating Wirebonded CoB on Rigid-Flex

11-18-2021

There are many good reasons to use a chip on board (CoB) implementation. When this is combined with wirebonding and the use of rigid-flex PCB, challenges mount. An application that demands all three—CoB, wirebonding, and rigid-flex PCB—is a camera module that goes into a mobile application, the sample design used to illustrate the design and analysis challenges in this article. If you are not aware of and prepared for the potential pitfalls, it is highly likely that your project could fall short or even fail.

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All Systems Go! Signal Integrity Signoff of 3D-IC Systems

10-14-2021

3D-ICs meet the demand for integration of disaggregated system-on-chip (SoC) architecture built from multiple chiplets and heterogeneous architectures such as analog, digital, optoelectronics, and non-volatile memory.

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All Systems Go! Comprehensive Thermal Analysis of a System Design

09-23-2021

In recent years, driven by the demand for smarter electronics, device designers have witnessed enormous scaling of large and hyperscale integrated circuits (ICs) and embraced development directions toward high density and reliability. These devices have increasingly higher thermal performance requirements—both transient and steady-state—and meeting them is becoming increasingly complex and time consuming.

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All Systems Go! Challenges in Analyzing Today’s Hyperconnected Systems

07-26-2021

Today’s data-thirsty world is looking forward to the next-generation communication systems beyond 5G, the promise of massive connectivity to the internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services made possible through innovative and resilient technologies. The exponential growth in data speed and networking has introduced numerous design and analysis challenges across a system design. Design teams are challenged to deliver new, differentiated products faster and more efficiently, despite the ever-growing complexity of silicon, package, board, and software for many complex applications in the hyperscale computing, automotive, mobile, aerospace, and defense markets.

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All Systems Go!: Thermal Compliance of 3D-IC

06-24-2021

In the packaging world, we have been designing heterogeneously integrated multi-chip products for decades. As we know, smaller process nodes enable higher frequencies and save on die area. However, for minimizing the system size, we need to use advanced packaging technologies.

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All Systems Go! Ensuring Signal Integrity of DDR5 Interface

05-25-2021

The double data rate synchronous dynamic random-access memory (DDR SDRAM) has evolved from a data rate of 0.4 Gbps to the next generation, DDR5, scaling to 6.4 Gbps. With DDR5, we can achieve higher bandwidth using less power per bit transferred, enabling us to do more computing on larger data sets.

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All Systems Go! EM Analysis for Today’s System-Level Designs

04-30-2021

There are two main reasons to do EM analysis: to see if the signals in the design will meet your performance specifications, and to see whether the design has unintended EM interactions in the circuit or system. Since domain-level requirements vary, not all EM solvers are the same.

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