Today’s data-thirsty world is looking forward to the next-generation communication systems beyond 5G, the promise of massive connectivity to the internet with extreme capacity, coverage, reliability, and ultra-low latency, enabling a wide range of new services made possible through innovative and resilient technologies. The exponential growth in data speed and networking has introduced numerous design and analysis challenges across a system design. Design teams are challenged to deliver new, differentiated products faster and more efficiently, despite the ever-growing complexity of silicon, package, board, and software for many complex applications in the hyperscale computing, automotive, mobile, aerospace, and defense markets.
Design flows are fragmented across chip, package, board, and system levels, making end-to-end simulation harder. An accurate 3D model is the most accurate and reliable method to achieve structure optimization and high-speed compliance of the complex structures found in silicon interposers, rigid-flex PCBs, stacked-die IC packages, connectors, and cables. A high-fidelity interconnect design is a critical factor for high-speed signaling, such as 112G SerDes interfaces that are highly susceptible to any change in impedance that negatively impacts the bit error rate. Optimization entails extensive what-if analyses including dozens of complex extractions and simulations. The alternative method using legacy tools requires users to partition a design, do piecemeal modeling and analyses, and stitch the results together. This method introduces accuracy loss, user errors, and risk. In addition, the need to merge mechanical structures such as cables and connectors with the system design to create one comprehensive model and simulate as a single piece cannot be accomplished.
Figure 1: Real measurement from PAM4 silicon (left) compared with modeled output (right).
While true 3D modeling and analysis of such structures are difficult for current legacy tools to handle, simulating them with board and IC packages cannot be done without parallelization for scalability and simulation performance. If the parallelization can work on computers in the cloud with a smaller memory footprint, it becomes cost-effective, too.
Driven by the inability of legacy tools to perform accurate system-level modeling and performance optimization beyond the module level while minimizing electromagnetic (EM) interference and radiation, designers are forced to use a methodology that includes several rounds of prototyping and trips to an anechoic chamber. On the other hand, a competent FDTD solver could significantly cut the prototyping and anechoic chamber runs, reserving the chamber test for the final compliance.
On the analysis front, resolving EM, electronic, signal, thermal, and electromechanical challenges are critical to ensure the performance of any electronic system. EM analysis is imperative to verify if signals in the design meet performance specifications and whether the design has unintended EM interactions in the circuit. While it is advantageous to use domain-optimized (chip, package, board, and system) EM tools, piecemealing the EM simulation can lead to losses of simulation fidelity, and manually stitching hundreds of ports can be error prone and time-consuming. If simulation tools cannot economically scale, that is a major problem. Besides, identifying the model file that represents the latest layout is cumbersome for designers due to concurrent revisions. Designers struggle to keep up with the sheer quantity of generated S-parameter files, and there’s no assurance that the optimized layout is the same as the one sent for manufacturing. With complex 3D structures like connectors, cables, and backplanes, true 3D modeling and system-level analysis with adequate scalability and performance are key.
Figure 2: EM modeling results using PAM4 four-voltage-level signaling.
Thermal effects on electrical performance and power have been key concerns for the mobile and data center markets for a decade. Higher data rates (switching frequencies) such as 400G and 800G Ethernet generate more current and, hence, heat. How the heat is dissipated/transferred out of the system depends on the environmental conditions. The highly inter-related nature of these two problems forces them to be solved together, and none of the legacy solutions can. What is needed is a thermal solver that supports not only static and transient thermal analysis, conduction (finite element methods (FEM)), and convection (computational fluid dynamics (CFD) approaches, with integrated intra-system electrothermal and voltage drop analyses).
Figure 3: Simultaneous thermal and electrical analysis for ICs, packages, boards, and systems.
Figure 4: Combination of FEM for solid structures with CFD for airflow.
To truly enable system-level analysis without breaking the analysis into pieces, you need computational software that is fast and can scale into the cloud or on-premises data centers to get essentially unlimited capacity and a speedup of up to 10X.
Figure 5: Example of electrothermal co-simulation results.
The combination of higher data rates, lower power supply voltages, smaller geometries, and denser circuits and components including packages, PCBs, connectors, cables, and backplanes requires accurate signal integrity analysis to ensure functionality and regulatory compliance. Stacked die and packages, higher pin counts, and greater electrical performance constraints add to the challenge. One of the biggest challenges with analyzing signal integrity is cross-dependency between power, temperature, and IR drops. Unlike the traditional power integrity (PI) analysis, which assumes an ideal power delivery network (PDN), power-aware SI analysis uses non-ideal signals and non-ideal PDN, optimizing the simultaneously switching noise (SSN) and resulting in better jitter performance and timing constraints.
An effective and efficient solution takes an integrated set of tools and flows to addresses scalability, performance, and accuracy in the design and analysis of systems, both at the component level and at the system level. For today’s system-level high-frequency product designs, users need SoC and system-level tools that support the following:
- Highest level of built-in accuracy
- Co-design and co-simulation
- A single well-integrated flow with built-in inter-domain data transfer
- Minimum set-up time
- Facilitates collaboration across design teams
What is needed is an end-to-end analysis solution that works seamlessly with a full system-level analysis solution. Operating early in the design cycle allows for “what if” scenario exploration, sets more accurate design constraints, and reduces design iterations.
Suketu Desai is senior director of product engineering, Multiphysics System Analysis Group, Cadence Design Systems, Inc.
Be sure to visit I-007eBooks to download your copy of Cadence Design Systems' micro eBook today:
The System Designer’s Guide to… System Analysis: Electromagnetic Interference and Thermal Analysis of Electronic Systems
And don't miss the companion guide, "The Cadence System Design Solutions Guide," available for download as well.
Thermal Analysis of Electronic Systems