All Systems Go! Ensuring Signal Integrity of DDR5 Interface

Brad_Griffin_300.jpgThe double data rate synchronous dynamic random-access memory (DDR SDRAM) has evolved from a data rate of 0.4 Gbps to the next generation, DDR5, scaling to 6.4 Gbps. With DDR5, we can achieve higher bandwidth using less power per bit transferred, enabling us to do more computing on larger data sets. DDR5 satisfies high-performance memory demands driven by the data-centric next-generation intelligent products. With significant performance improvements and power gains over its predecessors, DDR5 also introduces several design considerations concerning higher speeds and lower voltages that raise a new set of signal integrity challenges to an integral part of the DDR interface, the package design. 

We must be conscientious of package design of the memory controller and must perform an exhaustive analysis to ensure that the chips will work within the full system. An effective full-system analysis can be achieved by using an efficient and proven methodology that is evolving all the time to be able to support all the various challenges of DDR5. I will discuss this in detail in the subsequent sections. 

The DDRx speed continues to be faster, and there are many challenges about implementing a DDR interface successfully within a system. Data transmission between the memory controller and the DDR memory module, as per the JEDEC specification for bit-error-rate, eye mask, timing, and jitter is a rigorous task for high-speed operations. DDR5 signaling speed has reached 6.4 Gbps, equivalent to the traditional SerDes speed. This is a significant data rate increase for DRAM modules over conventional single-ended data transferring DIMMs. Dealing with a parallel bus in a single-ended mode at this speed is arduous. Simultaneous switching of multiple bits on the data bus and command/address bus adds to this challenge and makes it strenuous to keep a stable power in the power delivery network. 

Simultaneous switching noise could impact the power and ground associated with it when dealing with lower voltages in DDR5. DDR4 was a 1.2 voltage swing, and DDR5 is a 1.1 voltage swing. Low power gives less margin to absorb the impact from simultaneous switching noise (SSN). Therefore, managing the bit error rate becomes very challenging, and we need sophisticated design practices to meet the JDEC specifications.

cadence-1.jpg Figure 1: SI attributes to consider with DDR5 interfaces.

Optimizing the memory controller package alone is not adequate to realize the desired performance. We must take care to follow the recommended board design practices as well. We need to model the entire channel from the DDR controller to the memory and optimize it for high-speed transmission to enable the product designers to produce a reliable DDR5 channel. Simulation gives insight in advance and reduces last-minute surprises. When simulating a design, ensure that different signal integrity parameters like crosstalk, reflection, eye diagram, overshoot, undershoot, and the rest are per the JEDEC specifications. These parameters need to be optimized for the high-density silicon package breakout, parallel data, command/address bus routing, and power mesh. 

During high-density fanout, we might need to take a narrow track between the pins or breakout via and signal fanout can route over the anti-pad clearance that can cause impedance discontinuities in the breakout area causing routing over void SI issues.  So, we need to plan the breakout area considering all these aspects to produce a better DDR5 channel. There is a lot of other factors as well to consider when designing a DDR5 interface. 

cadence-2.jpg Figure 2: Building system-level simulation topology.

Even the best DDR IP cannot overcome a poor package design, and at the same time, a poor package design can muddle the entire system. As we discussed earlier, a full channel simulation is essential for optimizing high-speed interfaces like DDR5. Look at the schematics in Figure 2, starting at the transmitter, the DDR channel starts from the DDR controller through the package going to the motherboard and entering the memory chip through DIMM connector/PCB and memory package. The memory controller can potentially have a decision feedback equalization module to capture the equalizations to the redistribution layer at the chip level and then to the package design.

All of these pieces are connected through a connector to a DIMM module. It is essential to ensure that this plug and play pieces work together with the system especially at a minimum speed of 4.8 Gbps. Traditionally, these different elements in the DDR channel interface were modeled and extracted using non-full wave 3D field solvers or a hybrid solver to be able to extract that DDR interface and create an S-parameter that would plug into the system. We can still consider this methodology early in the design cycle, however, simulating a 4.8 Gbps+ interface requires a full-wave 3D accuracy to get more reliability and confidence in the design. Modeling a full DDR interface in a large package is a huge simulation, and a 3D model is required to determine if the full DDR interface meets the JEDEC specification and to build each block of the system with speed and accuracy.

Cadence-3.jpg 

The selection of the right tools and methodology plays a key role in determining the success of the product. Starting with the right package design tools, we must select a technology that is consistent, proven over the years and trusted by most of the semiconductor companies. The tool must be flexible and capable of supporting different types of packages like wire bond PBGA, flip-chip BGA Thin/Thick Hybrid, and so on. The next step is to supplement with in-design analysis on the package. A true 3D modeling of the DDR interface is the key to get accurate system-level simulations and a final signoff with accurate modeling of transceiver equalization and interconnect models. Using certified, production-proven and integrated solutions from a single vendor for extraction and multi-million-bit simulation will help achieve the bit-error-rate simulations to an effective and a signoff DDR5 interface in the package with the highest quality and confidence.

Brad Griffin is a product management group director for the Multiphysics System Analysis Group at Cadence Design Systems Inc.

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2021

All Systems Go! Ensuring Signal Integrity of DDR5 Interface

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