EIPC Summer Conference: Day 2
Refreshed after an excellent conference dinner, and for most, a good night’s sleep, delegates returned for the second day of the EIPC Summer Conference in Berlin, continuing the theme of improving profitability through technical leadership and innovation to meet future market requirements, with sessions on materials and processes for high performance PCBs and advanced material testing strategies to meet OEM and ODM needs.
The materials and processes session was moderated by Professor Martin Goosey, Vice President, Technology at EIPC, and his first speaker was Martyn Gaudion, MD of Polar Instruments with a presentation entitled “Fast and Fine: addressing the challenges of impedance measurement on fine line traces.” Beginning with his customary declaration that “All models are wrong, but some of them are useful,” and with reference to the differences between “lossless” and “lossy” transmission lines, he explained that fabricators building designs for frequencies below 2GHz typically worked on the basis of lossless characteristic impedance Zo, whereas in designs of 2GHz and above the focus shifted towards measurement of insertion loss in the transmission line. There was a grey area where lines operating at moderate speeds experienced low-frequency losses because of fine line geometries, and the correlation of measured impedance with modelled results was not as precise as would be expected. From a few MHz to 2GHz, losses were small enough to ignore, and impedance could appear the same at any point along the line. In fact, 100% of the signal energy was transmitted along the line and any losses were primarily the result of mismatch of input and output impedance causing reflections. From 2GHz upwards, losses in copper and dielectric absorbed power from the signal and, as frequency increased, proportionately less signal was transmitted. When attempting to make a measurement of the characteristic impedance of a fine line, these accumulated DC and AC resistances caused a slope on the TDR trace so that the observed value varied depending whereabouts on the trace it was measured. Launch point extrapolation was a method of computing the instantaneous or incident impedance by removing the DC and AC resistance effects, enabling better correlation between field solver modelled and actual measured values.
Dominique Garmy, from DuPont Circuit and Packaging Materials discussed flexible circuit materials for high-temperature environments, commenting that although an increasing number of automotive, military, aerospace, oil and gas applications required flexible circuits capable of withstanding high service temperatures, there had been a shortage of suitable materials and a lack of good test methods for evaluating and qualifying them. Failure mechanisms fell into three categories: adhesion loss, between copper and dielectric or between dielectric layers; embrittlement of dielectric; and embrittlement of copper. In most cases flexible circuit dielectrics were the first to fail, thermoset adhesives being more sensitive to embrittlement than polyimide films. One UL rating for high temperatures was based on relative thermal index (RTI), determined by loss of tensile strength and dielectric strength with long term thermal ageing. Samples were tested without copper so the test did not relate to any copper-adhesion loss and by itself was not a good measure of the capability of a copper clad laminate. The other UL test was maximum operating temperature (MOT), primarily determined by loss of copper adhesion after accelerated heat aging. The IPC service temperature test IPC-TM 2.6.21B appeared to work well for testing copper clad laminates but not as well for bondplies and coverlays. A new coverlay test, based on bend-testing, had been demonstrated, and overall results clearly indicated that all-polyimide clads, bondplies and coverlays provided the highest service temperature performance, with results close to industry experience. DuPont would continue to refine the new coverlay service temperature test and proposed to recommend its adoption by IPC.
Eric McLean, sales manager at Cambridge Nanotherm in the UK, discussed a nanoceramic dielectric designed to expand the performance of metal-in-board PCBs. Traditional metal-in-board substrates were limited in performance by the use of polymeric materials to provide electrical insulation and mechanical adhesion between the copper conductor layer and the aluminium core. These polymers had significant thermal resistance and a low degradation temperature which tended to restrict their continuous operating temperature to below 150°C.
McLean described an innovative electrolytic process for converting the surface of aluminium to a dense, strongly adherent, layer of nanoceramic, the dielectric properties of which were better than those of sintered alumina, such that only a 10 micron layer was required for electrical insulation. “It’s alumina, but not as you know it!” Since the nanoceramic material had good thermal conductivity, the thermal resistance of the coating, quoted as 0.014°C.cm2/W, was the lowest currently available. Direct metallisation of the nanoceramic eliminated all organic constituents in the construction and enabled sustained operation at temperatures above 250°C. Because the nanoceramic was formed by a self-levelling conversion process, through and blind vias could be straightforwardly coated, irrespective of aspect ratio, so that double-sided circuits could readily be fabricated. And the coating was capable of withstanding bending without cracking or peeling, so that substrates could be post-formed into three-dimensional shapes. Application examples included LED chip-on-board modules, LED light engines, power amplifiers and switching power supplies.
Hiroyoshi Tojima, from MEC Company in Japan, described how an anisotropic etching technology developed for chip-on-film applications was being adapted for HDI and packaging applications. In chip-on-film devices such as the drivers for LCD displays, 10 micron lines and spaces on 8 micron foil were typical and satisfactory definition was difficult to achieve by conventional subtractive techniques because of lateral attack by the etchant. Semi-additive techniques gave better conductor cross-section but were comparatively complex and higher in process cost. Physical limitations were the non-planarity of plated conductors and a tendency for undercut at the flash-etching stage to initiate peeling-off of fine conductor features. So there was a technical demand for an anisotropic subtractive process, to which MEC Company had responded by developing an additive for cupric chloride based etchant, which formed a protective film at the sidewall and inhibited lateral etching, giving a remarkable improvement in etch factor. Although etching machine set-up was critical and there was a narrow operating window, the process had established almost 100% market share with Japanese and Korean chip-on-film manufacturers. So it was logical to develop a variant of the process for HDI and packaging manufacture, where the line width demands were not as crucial but panel sizes were much larger and double-sided etching was required. Another complication was that the copper was likely built up in layers of material of different origin, for example: foil copper, catalyst, electroless copper, electroplated copper, all of which could have different etching characteristics. The target was to achieve an etch factor better than 4.0 on 40 micron lines and spaces in 18 micron copper. Extensive trials had been carried out over a wide range of operating parameters and circuit geometries, and it had been shown that the addition of only 5% of MEC’s proprietary additive in standard etching equipment achieved the target etch factor whilst reducing contact time by 10–15%.
Hiroyoshi Tojima, having demonstrated what could be achieved by state-of-the-art subtractive processing, Multiline International Europe MD and former EIPC chairman Paul Waldner came from the opposite direction to talk additive! Many had tried and failed in the quest for a process that would open up opportunities in full-additive circuit fabrication, and adhesion of metal to substrate had been a problem that had not been satisfactorily overcome. With the rapid emergence of PCB technologies based on ultra-thin bendable and stretchable substrates, how could copper be made to stick reliably?
Waldner presented a paper written by Alex Richardson, VP of Global Strategic Operations for eSurface, entitled: “A novel approach for applying metallization to ultra-thin substrates,” introducing an innovative photosensitive catalyst with the proprietary name of Covaler which, besides PCB manufacture, had a wide range of applications including decorative metallisation, wearable technology, semiconductor packaging, medical, military, automotive, solar, and other industrial uses. In PCB fabrication, eSurface’s Covaler had been specifically formulated for inner and outer circuit board layer constructions, flexible circuits and interposers. Claimed to be a breakthrough enabler, it was compatible with the majority of industry-standard base materials and opened up opportunities for many non-traditional materials. Applied as a surface treatment using a conventional wet process line, the Covaler bonded to the substrate surface and became autocatalytic to electroless copper upon exposure to UV light, so could be used directly to fabricate full-additive circuitry. Alternatively, it could be used as the base for all-over electroless copper plating in a semi-additive process capable of very fine-line resolution.
Alun Morgan returned to moderate the final conference session, this time in his role as project facilitator and European representative for the High Density Packaging User Group, HDPUG. He introduced HDPUG as a non-profit trade organisation whose member companies were involved in the supply chain of producing products utilising high-density electronic packages. HDPUG was entirely member-driven, its members deciding what technical areas to pursue and what topics to investigate, in order to stay focused on the most important issues affecting the electronics manufacturing industry. Its stated mission was to reduce the costs and risks for the electronics industry by improving cooperation between system integrators, contract assembly manufacturers and suppliers in the high-density packaging development and design process, using member resources, supplemented by a small staff. HDPUG’s activities revolved around the spirit of cooperative R&D, where members could gain much more by sharing resources and expertise to address issues of common interest than by duplicating work in each member company. This enabled major problems and global technical issues to be resolved in a fraction of the time and at a fraction of the cost it would take for companies to do it individually. The group was focused on the characterisation and reliability of electronic assemblies and sub-assemblies. As technology progressed, new materials and new processes were being developed, and new requirements, for example environmental regulations, were influencing how electronic assemblies were built. It was in the interest of all parties that products built with these new materials and processes were reliable and cost effective, and HDPUG ran projects to evaluate and understand the effects of material and process change. Twenty-eight R&D projects had been completed in the last three years, and 27 were currently in progress.
Morgan described the process by which projects were conceived, defined, approved and executed, using the Harsh Use Environment Alloy Evaluation project as an example, and then welcomed Marika Immonen from TTM Technologies to give an update on the second phase of the Optoelectronic project: “Optoelectronic Interconnect—preferred solution for short-range interconnect?” This project, which involved a total of 31 contributing companies, had begun five years previously with the objective of evaluating the feasibility of optical waveguide based technologies on PCBs, determining performance benefits and limitations using polymer waveguides and fibres for 1–2 metre links. The focus was on optical fibre and waveguide link characteristics, practical connectivity options and end-to-end link implementations. The first phase, in which test vehicles with multiple waveguide components had been used to verify the practicality of using optical fibres for short-range interconnect, had been completed. The second phase was at the definition stage, and proposed to use the viable building blocks from Phase 1 to build a more complex system-level demonstrator with end-to-end optical links. Ms. Immonen gave a comprehensive overview of the design rules and interconnection models for the OE2 demonstrator, which would have a combination of free-standing flexible waveguides, embedded glass wave guides and embedded polymer waveguides.
Final speaker of the day was Bill Birch from PWB Interconnect Solutions, and if there had been a prize for the longest title of the conference, he would have been a sure winner with “Quantifying and benchmarking new PWB materials reliability, electrical performance and thermal properties following exposure to today’s lead free assembly environment.” A long-term corporate member of HDPUG, Birch had been engaged in an ongoing programme to evaluate material reliability. “Designers can get carried away and let electrical properties take precedence over reliability. We need a balance of electrical performance with reliability and manufacturability.” Working with HDPUG to build up a database of PCB material properties, he had characterised 98 materials to date and there were 22 new materials currently being evaluated. Birch reviewed the results of Phase 3 of the HDPUG Materials Reliability study, in which twelve materials—two high-Tg FR4, six halogen-free and four high-speed—were each constructed in two resin contents as a 20-layer test vehicle, 2.5 mm thick, with 0.25 mm drilled holes. For consistency, all had been fabricated simultaneously by the same manufacturer. The test vehicles were all subjected to six reflow cycles at 260°C, then tested using IST and DELAM procedures. All of the materials claimed to be lead-free compatible, but not all were! Fifteen of 24 delaminated in the 0.8 mm grid area and eight of 24 in the 1.0 mm grid area, whereas all had passed the old IPC solder-float test—dating from 1961 and clearly not representative of current assembly conditions. The delamination failures observed raised questions which needed to be answered by laminate manufacturers. They tended to be cohesive failures across the central zone of the construction, and compromised the critical glass-resin interface. The question of “what’s good enough?” to satisfy the customer’s needs would always be the determining factor, and quantifying the overall PTH via reliability performance in terms of a materials ranking proved difficult, because of the complicating effect of cohesive material damage.
Alun Morgan brought the proceedings to a close. Another in a long series of highly successful and informative EIPC conferences, drawing the industry together with a well-selected programme of technical presentations of current relevance and interest, interwoven with an abundance of networking opportunities and a very positive community spirit. Thanking all presenters for their contribution and delegates for their attention and support, he especially acknowledged EIPC Executive Director Kirsten Smit-Westenberg and Event Manager Sonja Derhaag for their superbly professional organisation of the occasion.
I am once again grateful to Alun Morgan for allowing me to use his photographs.
To read EIPC Summer Conference review, Day 1, click here.
Based in the UK, Pete Starkey is technical editor for I-Connect007. He has more than 30 years experience in the PCB industry, with a background in process development, technical service and technical sales.