Cannonball Stack for Conductor Roughness Modeling

Reading time ( words)

In the GB/s regime, accurate modeling of conductor losses is a precursor to successful high-speed serial link designs. Failure to model roughness effects can ruin your day. For example, Figure 1 shows the simulated total loss of a 40-inch PCB trace without roughness compared to measured data. Total loss is the sum of dielectric and conductor losses. As can be seen, with just -3dB delta in insertion loss between simulated and measured data at 12.5 GHz, there is half the eye height opening with rough copper at 25GB/s.

According to Wikipedia, close-packing of equal spheres is defined as “a dense arrangement of congruent spheres in an infinite, regular arrangement (or lattice)." The cubic close-packed and hexagonal close-packed are examples of two regular lattices. The cannonball stack is an example of a cubic close-packing of equal spheres, and is the basis of modeling the surface roughness of a conductor in this article.

So, what do cannonballs have to do with modeling copper roughness anyway? Well, other than sharing the principle of close packing of equal spheres, and having a cool name, not very much.


In PCB construction, there is no such thing as a perfectly smooth conductor surface. There is always some degree of roughness that promotes adhesion to the dielectric material. Unfortunately this roughness also contributes to additional conductor loss.

Electro-deposited (ED) copper is widely used in the PCB industry. The manufacturing process sees a large rotating drum, made of polished stainless steel or titanium, which is partially submerged in a bath of copper sulfate solution. The cathode terminal is attached to the drum, while the anode terminal is submerged in the solution. A DC voltage supplies the anode and cathode with the correct polarity.

As the drum slowly rotates, copper is deposited onto it. A finished sheet of ED copper foil has two sides. The matte side faces the copper sulfate bath, while the drum side faces the rotating drum. Consequently, the drum side is always smoother than the matte side.

The matte side is usually attached to the prepreg sheets, prior to final pressing and curing, to form the core laminate. Prepreg is the term commonly used for a weave of glass fiber yarns pre-impregnated with resin which is only partially cured. To enhance adhesion, the matte side has additional treatment applied to roughen the surface. For high frequency boards, sometimes the drum side of the foil is laminated to the core. In this case it is referred to as reversed treated (RT) foil. Even after treatment, it is still smoother than standard treated foils.

To read this article, which appeared in the May 2015 issue of The PCB Design Magazine, click here.



Suggested Items

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.

DFM 101: PCB Materials

04/30/2021 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is understanding the cost drivers in the PCB manufacturing process. This article is the first in a series that will discuss these cost drivers (from the PCB manufacturer’s perspective) and the design decisions that will impact product reliability.

Eliminating ‘Garbage In, Garbage Out’ With Checks and Balances

03/26/2021 | Nick Barbin, Optimum Design Associates
The proverbial saying “garbage in, garbage out” holds true in the electronic product development world. PCB designers stand squarely in the middle of a busy information intersection flowing with inputs and outputs. Missing or bad information at the beginning of a design project will undoubtedly lead to board re-spins, increased costs, and most importantly, a delayed product release. The same can be said about the PCB designer who doesn’t provide a fully checked and comprehensive data package to the downstream manufacturers, i.e., “throwing it over the fence.”

Copyright © 2021 I-Connect007. All rights reserved.