Power distribution networks (PDN) are becoming an important topic. Many engineers are finding that properly designing the power supplies and providing adequate decoupling for devices is a challenge, especially since devices are switching faster and dimensions are shrinking. Engineers often focus on discrete decoupling capacitors placed local to switching devices in hopes of providing the required capacitance for these high current demands. One of the more overlooked items of the power distribution system is the PCB, and how it contributes to the power distribution system’s ability to decouple the switching devices. The following experiment will outline a basic principle that should be in mind when designing a stack-up and PDN.

Basic PDN Model

A basic PDN includes the voltage regulator model (VRM), the discrete decoupling capacitors, the PCB, and any on-die capacitance formed on the IC or device. Each one of these components could be written about separately, but it is the PCB that will be focused on; specifically the effective decoupling radius.[2]

When a device is active, it will require current. The type of device (process size), load on the I/O drivers, and how the device is operated, all have an effect on the current required, among others. When the device demands current, it flows through the complex impedance of the PDN and causes a ripple voltage to appear. This transient current is drawn from a variety of sources including the local on-die decoupling capacitance, the PCB, the discrete capacitors, and finally the VRM.[1] The edge rate of this switching current is extremely important when trying to calculate how effective the PDN will be in suppressing the ripple voltage. The switching edge can be dissected into a variety of harmonic sine waves at decreasing amplitude described by a Fourier series equation. It is here that we discover the importance of the PCB, and its role in the PDN.

The simplest way to represent a PCB is a distributed RLC network. Capacitance is formed by the copper layers and the dielectric between them. Inductance is formed by the loop area between the layers, and the resistance is formed by the cross sectional area and length of the copper planes.

## Alternatives to Simulation

04/23/2021 | Dan Beeker, NXP Semiconductors
We are living in an age where the demands on electronic product designs are constantly evolving. The IC technology and operating speeds continue to pose significant challenges for teams as they work to develop their products. The increased transistor switching speeds and less forgiving compliance standards make signal integrity and electro-magnetic compliance more difficult to achieve. The status quo seems to have become, “We expect to fail EMC testing.”

## Seven Tips for Your Next Stackup Design

02/01/2021 | Eric Bogatin, University of Colorado, Boulder
Rarely do we have the luxury of designing a board just for connectivity. When interconnects are not transparent, we must engineer them to reduce the noise they can generate. This is where design for signal integrity, power integrity and EMC—collectively high-speed digital engineering—are so important. Eric Bogatin offers seven tips for stackup design.

## Just Ask Heidi Barnes: The Exclusive Compilation

01/15/2021 | I-Connect007 Editorial Team
We asked for your questions for Keysight Technologies' Heidi Barnes, and you took us up on it! We know you all enjoyed reading these questions and answers, so we’ve compiled all of them into one article for easy reference. We hope you enjoy having another bite at the apple.