Averatek Pushing Boundaries of Additive and Semi-Additive Processes


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I recently attended the IEEE International Microwave Symposium show in Atlanta, my first trade show since IPC APEX EXPO and DesignCon in early 2020. That seems like 10 years ago, doesn’t it?

I met with Tara Dunn, I-Connect007 columnist and VP of marketing and business development for Averatek. We sat down at the show and discussed the past year and a half, and after joking about how we felt like we were on an episode of The Twilight Zone, Tara gave me an update on Averatek’s continuing research into additive and semi-additive technologies.

Andy Shaughnessy: I’m here at IMS show in Atlanta with Tara Dunn, columnist and VP of marketing and business development for Averatek. How are things going?

Tara Dunn: Great. It’s great to be back at a trade show and see people in person.

Shaughnessy: And you were just telling me about some of the new things going on at Averatek. It sounds pretty exciting.

Dunn: It’s very exciting right now. We’ve got three commercial fabricators that are currently building with A-SAP™, our Averatek semi-additive PCB process. This is opening up capacity for PCB designers to start working with lines as small as 25 microns and below.

Shaughnessy: Tell us about some of the advantages of the additive and semi-additive processes.

Dunn: At first glance, probably the most obvious is the improved density that you can get with your circuit traces being at 25 microns, instead of being limited at 75 microns. We just did a redesign project where we took a reference design that was eight layers, and it had five signal layers, and two power and ground. We redesigned that to four layers total—two signals and two power layers—which was great. I mean, that’s a significant improvement going from eight layers to four layers, it greatly simplifies the design. And then, at the same time, we started getting into the signal integrity analysis of that and started to understand that perhaps there are other benefits to be realized beyond layer count reduction.  We are currently evaluating the potential power delivery improvements that could be realized with an adjustment to 6 layers rather than 4. This would result in both a layer count reduction and improved performance.  There are a lot of exciting things to consider.   

Shaughnessy: Right. And one of the things I understand about the additive processes is that the traces are straight, not trapezoidal?

Dunn: Yes. The trace edges are straight up and down, and they’re actually defined by the photoresist rather than by an etch process. So, we’re able to control that straight up and down feature of it, like you said, but also control the line width and the height to a much greater degree than we’re able to do with subtractive etch processes.

Shaughnessy: That could really help impedances at higher speeds.

Dunn: Exactly. Being able to more tightly control that impedance is a win for everybody.

Shaughnessy: You mentioned that you have some research going on with Eric Bogatin and his class at University of Colorado–Boulder?

Dunn: We’re working on a series of three white papers with Eric that specifically look at different signal integrity parameters. What happens when you start having these finer traces and you’re putting them closer together? What do the models look like? How do you deal with that as a designer? I’m really trying to come out with different tools to help PCB designers understand how to best implement the A-SAP process. There will be some applications where you want all your lines to be 25-micron line and space, and you want to shrink that as far as you can.

In other cases, there’s going to be reasons not to do that and maybe use it in a certain specific area of the design. Not all the layers have to be A-SAP, so we can use those in combination with subtractive etch layers, as well. We are doing a lot of modeling and analysis, trying to understand exactly what PCB designers should expect.

Shaughnessy: Yes, designers will probably need some guidance on that. They won’t want to over-constrain if they don’t need to.

Dunn: Exactly. There’s a difference between taking that 25-micron line and space over the same distance, and the impact it has, and taking a 25-micron line and space over a shorter distance. It’s about trying to find where those rules and the break points will be for designers; we are working diligently at it right now.

Shaughnessy: I read your interview with Cherie Litson, an instructor with EPTAC. She’s already pretty well-versed in additive processing.

Dunn: She’s very excited about the technology. Cherie has spent quite a bit of time learning, talking, asking questions, and she’s got a very creative mind. She’s coming up with some really good opportunities and ways to apply the technology.

Shaughnessy: Anything else you want to mention?

Dunn: I don’t think so other than I’m looking forward to the fall. We’ll be doing a lot of speaking at the trade shows and conferences, and I’m looking forward to seeing everybody.

Shaughnessy: I’ve definitely missed it. We’ve been gone for what, 15 months?

Dunn: Who would’ve ever thought? It’s great to be back.

Shaughnessy: Thanks for doing this, Tara.

Dunn: Thank you, Andy. Great seeing you.

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