The Role of EDA Tools in Creating Fab Notes

Reading time ( words)

When discussing fab notes, there’s a lot of focus on what designers should and should not include in the package. But what is the role of EDA tools in this process, and can intelligent data formats streamline the tasks and help eliminate fab notes that are less than fantastic? In this interview, Pat McGoff, market development manager for Mentor, a Siemens Business, speaks frankly about fab notes and what EDA tool companies like Mentor can do to automate this process.

Andy Shaughnessy: What do you think are the biggest problems that PCB fabricators face regarding designers’ data packages?

Patrick McGoff: The biggest problem with the designer’s data packages is the confusion they often cause. Like other contract suppliers, PCB fabricators make every effort to be as accommodating as possible in terms of what kind of design data they will accept. I can remember when fabricators would take in a scanned image of a PCB and digitize it to reproduce the board.

Today, when we say, “Send us the Gerber files,” what we are really saying is “Send us the Gerber, drill, and netlist files, along with drill drawings, route drawings, stackup drawings, and notes,” and that’s just for the fabricators. Contract assembly providers need even more data and information. The problem with this legacy approach is that there are frequently discrepancies between the various files. The netlist file or drill file often does not match the Gerber data because they came from different systems and might not even reflect the correct revision of the design.

Shaughnessy: When there are problems with the fab notes and other data, what is the typical process that the fabricator goes through to resolve these issues? How does that impact the job?

McGoff: When a fabricator sees a discrepancy in the data provided, or if there is incomplete information, they put the job on hold until it can be resolved. The problem is that the delivery clock doesn’t start until the data package is complete and accepted. That five-day turn is sitting in the starting block waiting for the technical query (TQ) communication channel to do its thing. The CAM engineer notifies the manager of the issue, and the front-end manager notifies the salesperson, who then informs their point of contact at the customer side. Then, that information is conveyed to the designer, and only at this point can the correction and clarification process begin. All of this can easily take several days to resolve, so the designer pays for a five-day turn but gets the boards back in eight days.

It’s even more problematic if the fabricator misses a discrepancy in the data package and runs with the erroneous set. This raises a lot of questions, such as, “Which is the go-to file: the Gerber data, the drill file, or the netlist?” Do all your fabricators have the same understanding? Who is responsible for the scrap when that does happen? I believe the larger question should be, “Why would you ever leave the potential for that kind of discrepancy in your process?”

To read this entire interview, which appeared in the August 2020 issue of Design007 Magazine, click here.



Suggested Items

Turning ‘Garbage In, Garbage Out' into ‘Good In, Good Out’

03/23/2021 | Tamara Jovanovic, Happiest Baby
In the PCB design cycle, it is so easy to unintentionally introduce “garbage” into your system. Unless you have time to extensively check everything you bring in from an external source, it is very likely that something will not match up with your design data. In the end, this means you’ll have to put more work into your design and basically reverse-engineer a part that was supposed to save you time and effort.

Karen McConnell: Recipient of the IPC Raymond E. Pritchard Hall of Fame Award

03/11/2021 | Patty Goldman, I-Connect007
"I heard about IPC when I started a new job at UNISYS after graduating college. I moved from ASIC design to printed circuit boards," said Karen McConnell after being inducted into the Raymond E. Pritchard Hall of Fame. "At the time, in the late ’80s and early ’90s, there were rumors going around that printed circuit boards were going to disappear, and ASICs were going to take over the world. But something in printed circuit boards fascinated me. I minored in robotics in college as an electrical engineer and the data used to fabricate, assemble and test the boards is actually all robotic language. I was hooked."

The Key to Eliminating Bad Design Data: Constant Vigilance

03/09/2021 | I-Connect007 Editorial Team
The I-Connect007 editorial team recently met with Jen Kolar and Mark Thompson of Monsoon Solutions to discuss ways to eliminate bad data from the design process, whether that be from CAD libraries, parts vendors, chip makers, or customers themselves. They key in on some problems and obstacles that allow incorrect data into the design cycle, and then highlight possible solutions.

Copyright © 2021 I-Connect007. All rights reserved.