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Mentor Graphics Takes Best Paper Award at DesignCon
March 22, 2017 | Andy Shaughnessy, PCBDesign007Estimated reading time: 4 minutes
At DesignCon 2017, held February 1 - 2, I met with Dave Kohlmeier, senior product line director for Mentor Graphics. We discussed their Best Paper award and DesignCon sessions such as the Signal Integrity Boot Camp, as well as the new rigid-flex capabilities found in the HypeLynx suite.
Andy Shaughnessy: I'm here today with Dave Kohlmeier of Mentor Graphics, the senior product line director. Dave, what's going on at the show?
Dave Kohlmeier: We've been busy. So, let me give you a rundown on what's going on. I just came away from an awards ceremony where we won the DesignCon Best Paper Award for the paper we presented last year on the difference between using bit error rate and COM for channel analysis. Vladimir Dimitri Zadorov and several of our engineers were part of that. So we're pretty happy with that and that kind of is a good segue into what we're doing here.
We're really focusing on the ability to do channel compliance verification for these new protocols like PCI Express, Gen 3, Gen 4. It's really a very difficult process to validate a channel, and now that we have COM, the Channel Operating Margin, it allows engineers without modeling—without using driver and receiver models—to be able to qualify the interconnect between the transmitter and receiver. I think it's really the way forward. Since these protocols are so difficult to validate, this allows engineers a very clean, crisp way to look at a channel and verify it.
We introduced new technologies last year. We presented our paper last year on COM vs. the traditional eye diagram bit error rate efforts, and we're showing more of that today. Our latest release that came out, HyperLynx 9.4.1, actually has increased capability in that area for basically, almost push button validation using COM metrics, so that's a big one.
This year, we are presenting several papers again at DesignCon. We are focused hard on memory interfaces, DDR analysis. Also, we are talking about general operating margins, and PAM4, which is a new signaling level that is trying to stretch more bandwidth out of these interconnects, pulse-amplitude modulation 4-level. Each unit interval has more information because there are basically two bits of information. We're fully up to speed on that and supporting it, and we are also announcing some optimization methods for these SERDES channels.
Another thing, which was a huge success for us, was a signal integrity boot camp yesterday, on Tuesday, in Mentor’s Fremont office. We had almost a hundred registrants for that. The teacher was Dr. Eric Bogatin, and he's a pretty big attraction and does a great job of trying to get people to intuitively understand signal integrity and power integrity. So, we got some pretty awesome reviews from the people who went through that.
We also are introducing rigid-flex capabilities. Now, the full HyperLynx suite for SI or PI can deal with any kind of stack-up by area. So if you have a very complicated layout where you're using rigid sections and stiffener sections and flex circuits, we can model all of that now in the product. That’s a big piece for us.
We also have some capability for automatic pattern recognition, which allows you to identify areas that you might need to use 3D modeling in these SERDES channels. We can automatically identify those areas and then create a 3D cache, if you will, for the modeling of those areas. That's the big rundown.
Shaughnessy: I've noticed that about flex. I'm hearing more and more designers getting into flex. Because now there are tools that are actually designed for flex, so that's certainly opening things up, and rigid-flex too, because now there's rigid flex in everything.
Kohlmeier: That was a division-wide effort for us—to support all the way from schematic entry through PCB layout, through to analysis, to be able to cover and support rigid flex capabilities. Everything is shrinking, cell phones and everything else, and the way to get complexity into those smaller spaces is driving people to have this rigid flex combination. The prices are coming down a bit. Originally it was the price that kept people away from it, but because of the volumes of these devices, pricing is coming down.
Shaughnessy: Now you've got flex standards and EDA tools for flex, and flex is almost everywhere.
Kohlmeier: There are different things to worry about. For example, they have hatched ground planes, so instead of a solid plane they have basically put a hatch underneath so they can continue to be flexible. Now you need to be able to solve for impedances over hatched planes and things like that. It's not a straightforward thing. We had to invest quite a bit to get full support for rigid flex alone. It's been a record year for HyperLynx.
Shaughnessy: That's one thing I saw when I was working on the book with Happy Holden and Clyde Coombs. So many people use HyperLynx, even designers who aren’t using Mentor layout tools.
Kohlmeier: That's right. We support all CAD vendors. We are CAD-agnostic, so we support everybody.
Shaughnessy: Well, you guys have had a busy year.
Kohlmeier: It's been very busy. And I think it's going to be even busier. You can just tell by the energy here at the show. I just walked away from the keynote and it was focused on machine learning as part of doing your analysis. In order to do these new interconnects, we have to do simulation and analysis. We then have to do a lot of work on the data to understand trends. It's getting interesting…the room was absolutely packed, with lots of energy.
Shaughnessy: That’s great news. Dave, I appreciate your time today. Thank you.
Kohlmeier: Thanks, Andy.
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