Designers Notebook: Developing Panel Level Semiconductor Packaging

Semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface. The terminal size and pitch are often, however, far too small for conventional organic circuit board fabrication capability. To better accommodate die-to-substrate interface, several companies are successfully adopting wafer-level and panel-level package technologies.

Wafer Level Packaging
Silicon materials are commonly furnished in a 200-300 mm diameter wafer format sized to be compliant with the existing semiconductor fabrication infrastructure. Most commercial semiconductor manufacturers utilize these thin silicon wafers to provide a stable base for integrated circuit processing, but the silicon-based material has also proven to be an excellent choice for wafer-level packaging because it perfectly matches the CTE of the silicon die element(s) that will be mounted onto its surface.

Fabrication of the fan-out or fan-in/fan-out interposer is commonly performed within the semiconductor foundry environment. Die elements are arranged on the wafer’s surface in a row and column format, with the active surface facing up for wire-bond interconnect or face-down when furnished with alloy bump terminals.

The processes for via-hole ablation and metallization in the silicon material are very different from the basic semiconductor manufacturing processes. Metal deposition processes developed for the silicon-based interposer enable the redistribution of the very closely spaced terminals on the die element’s perimeter to a uniform and wider spaced array pattern that will enable a more efficient package substrate interface (Figure 1).

C_Solberg_Feb21_Fig1.jpg
Although the silicon wafer packaging process has proven robust and reliable, the cost associated with silicon-based interposer fabrication has been a primary detractor, and because the wafers are round, there is a great deal of surface area at the wafer perimeter that cannot be populated. In the effort to trim overall packaging expense several alternative panel-level packaging methodologies have emerged.

Panel Level Packaging

Both independently and through consortia of academia and industry, several viable solutions have evolved that provide the same fan-out and fan-in/fan-out interface capability. Panel-level packaging will continue to use silicon as a base, but alternative lower cost organic epoxy-glass laminate and panel formatted glass are viable options.

Silicon and Glass Panel Development

To gain better utilization of the silicon base, some companies have moved away from the traditional wafer level format to a square silicon or glass panel format where the individual die elements can be arranged in the same row and column format with minimal base material waste.

Silicon Interposer Base Material
To maximize assembly efficiency the base material can be furnished as 300 mm and 500 mm square panels, but some companies looking to maximize package assembly efficiencies are fabricating panels as large as 600 mm square.

Silicon-based interposer fabrication requires a rather specialized and complex sequence of processes that begin with via-hole formation. Although laser ablation can be adopted for forming the micro-via holes, the process most commonly employed for volume applications uses a deep reactive-ion etching (DRIE) process (often referred to as the “Bosch” process). This methodology can provide very small hole diameters that range between 5–20 microns. In preparation for conductor forming and via filling, a seed layer of copper or tungsten is applied to enable electroplating the additional copper required to complete the via-fill operation. Further pattern imaging and plating processes are engaged to provide interconnect features on the outer surfaces of the silicon substrate.

Glass Interposer Base Material
Significantly less costly than silicon, glass panels are being supplied by several companies specializing in manufacturing a physically durable glass with properties suitable for fan-out and/or fan-in package applications. The nominal CTE of the metalized glass panel is also a very close match to the silicon die (3 ppm/°C).

Glass is available in panel thicknesses that range from 50 μm to ≥700 μm, and the process differs significantly from silicon wafers because it will not require back grinding and polishing prior to via ablation and plating operations. The via-hole forming processes for glass include laser and electrostatic discharge as well as mechanical drilling using micro-sandblasting. Metallization on glass begins with a vapor deposition (PVD) process of copper or silver ink deposition to furnish the base for filling vias and interconnect circuitry.

High Tg, Low CTE Organic Base Material
One of the more promising materials for the high-density organic package substrate applications is promoted as an ultra-low CTE organic glass reinforced bismaleimide triazine (BT) based laminate.

While many organic dielectric materials have traditionally proven suitable for a broad range of wire-bond package applications, several leading suppliers have developed a more advanced laminate material that closely matches the very low thermal coefficient of expansion (CTE) of the silicon die element, as well as meeting the fine-line interconnect challenge for new generations of high I/O face-down mounted semiconductors. The manufacturer promises that the laminate will provide a more stable platform for mounting silicon-based semiconductor elements.

The design guidelines furnished in Table 1 relate to copper alloy via filling and conductor formation for the three base material candidates for panel-level semiconductor packaging. The geometries furnished were developed from research by the author and consensus among several colleagues involved in the technology.

C_Solberg_Feb21_Table1.jpg
The data shown may not reflect the capability of all suppliers in their respective categories, but supplier companies will generally furnish the designer with alternative design guidance related to their material sets and specific process capabilities. The supplier-developed interposer design guidelines will generally reflect factors derived from their experience, ensuring that they will likely furnish a reliable product with a high degree of quality and process yield.

Key Planning Issues for Panel Level Packaging
Assembly process methodologies will vary a great deal. Issues that will need to be resolved prior to beginning the development process include:

  • Availability of semiconductors prepared for face-down mounting
  • Establishing reliable sources for semiconductor elements
  • Specifying physical and environmental operating conditions
  • Defining package design constraints and process protocols
  • Stipulating electrical test method and post assembly inspection criteria

Semiconductor packaging methodology will continue to evolve, and market analysts project a steady growth in semiconductor package applications.

There is presently a global effort by members of SEMI (Semiconductor Equipment and Materials International) to develop standards for manufacturing panel-level packaging. The standards have already established panel size variations, thickness, as well as surface topography and panel warpage limitations.

IPC is currently in the formation stage to develop a standard guidance document for an organic-based panel format that is defined as “a wiring structure produced with a printed circuit board fabrication process that provides the final electrical interface between microelectronic devices and the underlying circuit structure.” Printed circuit manufacturing process characteristics include the use of square or rectangular panels with build-up circuit layers applied to both sides of the base using organic dielectric materials.

This column originally appeared in the February 2021 issue of Design007 Magazine.

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2021

Designers Notebook: Developing Panel Level Semiconductor Packaging

02-22-2021

While semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface.

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

01-29-2020

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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Designers Notebook: PCB Design and HD Semiconductor Packaging

01-15-2020

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

11-29-2018

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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Embedding Components, Part 3: Implementing Discrete Passive Devices

11-15-2018

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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Designers Notebook: Strategies for High-Density PCBs

01-01-2018

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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2017

Strategies for High-Density PCBs

11-27-2017

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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Embedding Components, Part 2

07-30-2017

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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Embedding Components, Part 1

06-30-2017

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

07-06-2016

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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Flexible and Rigid-Flex Circuit Design Principles, Part 6

05-26-2016

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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Flexible and Rigid-Flex Circuit Design Principles, Part 5

04-27-2016

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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Flexible and Rigid-Flex Circuit Design Principles, Part 4

03-30-2016

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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Flexible and Rigid-Flex Circuit Design Principles, Part 3

03-02-2016

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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Flex and Rigid-Flex Circuit Design Principles, Part 2

02-19-2016

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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Flex and Rigid-Flex Circuit Design Principles, Part 1

01-27-2016

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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2005

PCB Designers Notebook: Flexible Circuit Design

01-03-2005

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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