Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

Indium-based alloys are said to have very good thermal conductivity and ductility when compared to other low-temperature alloys. Bismuth-based alloys are also good for low-temperature soldering; however, thermal conductivity and ductility may not meet the expectation. Tin-bismuth and tin-bismuth-silver are the most common choices for low-melting solder pastes used for surface-mount assembly. The peak reflow temperatures provided by tin-bismuth alloys are low (160–170°C) compared to tin-silver-copper solders (220–230°C). The lower peak temperatures required for joining the LTS alloys are preferred when soldering thermally sensitive assemblies.

LTS has been a subject of research at Hewlett-Packard’s Electronic Assembly Development Center (EADC). The company believes that several benefits may derive from adopting this technology. They trust that a significant decrease in the peak reflow temperature during the reflow solder process will reduce physical stress to both the components and PCBs. HP further acknowledged that a single LTS alloy is not likely to be a universal solution for all product applications or suitable at all for products exposed to harsher operating environments and that extensive qualification testing of these materials is paramount.

Alloy selection is only the first step in developing a low-temperature soldering process. A suitable flux must be chosen for use in a solder paste, and the alloy-flux interaction must be evaluated. The ability of fluxes to activate at temperatures 20–30°C below the melting point of the alloy must be evaluated. In the case where different solder metallurgies have similar mechanical properties, the optimal metallurgy for a low-temperature process may be determined by the availability of the appropriate flux chemistry.

For the flux selection phase, there is no standard procedure for testing the activity of a solder flux. The degree of wetting in a system (solder, substrate, atmosphere, flux) may be characterized with a sessile spread test or by a wetting force measurement. The two tests are complementary. Each of the tests is said to involve a balancing of surface tensions at a three-phase junction. For an assessment of flux activity, a dynamic measurement is more appropriate than a static measurement. Thus, the wetting force measurement is preferred to the sessile spread measurement.

Intel is committed to implementing LTS for a broad number of products as well. The company noted that repeated exposure of array-configured components to the high peak temperature experienced during the tin-silver-copper (SAC) alloy solder reflow process often impacts the integrity of the terminal interface. It is not uncommon to experience package warp, causing momentary separation of the terminal from the circuit board’s land pattern. When the warp condition subsides, the solder interface is often compromised.

Intel has also performed extensive testing and evaluation of the LTS product offerings and anticipates implementation for a broad range of products. In addition to production cost savings from reduced energy consumption and environmental benefits, the company anticipates faster technology scaling for a wide range of applications.

Vern Solberg is an independent technical consultant based in Saratoga, California, specializing in SMT and microelectronics design and manufacturing technology.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

11-29-2018

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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Embedding Components, Part 3: Implementing Discrete Passive Devices

11-15-2018

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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Designers Notebook: Strategies for High-Density PCBs

01-01-2018

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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2017

Strategies for High-Density PCBs

11-27-2017

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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Embedding Components, Part 2

07-30-2017

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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Embedding Components, Part 1

06-30-2017

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

07-06-2016

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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Flexible and Rigid-Flex Circuit Design Principles, Part 6

05-26-2016

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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Flexible and Rigid-Flex Circuit Design Principles, Part 5

04-27-2016

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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Flexible and Rigid-Flex Circuit Design Principles, Part 4

03-30-2016

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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Flexible and Rigid-Flex Circuit Design Principles, Part 3

03-02-2016

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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Flex and Rigid-Flex Circuit Design Principles, Part 2

02-19-2016

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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Flex and Rigid-Flex Circuit Design Principles, Part 1

01-27-2016

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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2005

PCB Designers Notebook: Flexible Circuit Design

01-03-2005

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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