Designers Notebook: Developing Panel Level Semiconductor Packaging

Semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface. The terminal size and pitch are often, however, far too small for conventional organic circuit board fabrication capability. To better accommodate die-to-substrate interface, several companies are successfully adopting wafer-level and panel-level package technologies.

Wafer Level Packaging
Silicon materials are commonly furnished in a 200-300 mm diameter wafer format sized to be compliant with the existing semiconductor fabrication infrastructure. Most commercial semiconductor manufacturers utilize these thin silicon wafers to provide a stable base for integrated circuit processing, but the silicon-based material has also proven to be an excellent choice for wafer-level packaging because it perfectly matches the CTE of the silicon die element(s) that will be mounted onto its surface.

Fabrication of the fan-out or fan-in/fan-out interposer is commonly performed within the semiconductor foundry environment. Die elements are arranged on the wafer’s surface in a row and column format, with the active surface facing up for wire-bond interconnect or face-down when furnished with alloy bump terminals.

The processes for via-hole ablation and metallization in the silicon material are very different from the basic semiconductor manufacturing processes. Metal deposition processes developed for the silicon-based interposer enable the redistribution of the very closely spaced terminals on the die element’s perimeter to a uniform and wider spaced array pattern that will enable a more efficient package substrate interface (Figure 1).

Although the silicon wafer packaging process has proven robust and reliable, the cost associated with silicon-based interposer fabrication has been a primary detractor, and because the wafers are round, there is a great deal of surface area at the wafer perimeter that cannot be populated. In the effort to trim overall packaging expense several alternative panel-level packaging methodologies have emerged.

Panel Level Packaging

Both independently and through consortia of academia and industry, several viable solutions have evolved that provide the same fan-out and fan-in/fan-out interface capability. Panel-level packaging will continue to use silicon as a base, but alternative lower cost organic epoxy-glass laminate and panel formatted glass are viable options.

Silicon and Glass Panel Development

To gain better utilization of the silicon base, some companies have moved away from the traditional wafer level format to a square silicon or glass panel format where the individual die elements can be arranged in the same row and column format with minimal base material waste.

Silicon Interposer Base Material
To maximize assembly efficiency the base material can be furnished as 300 mm and 500 mm square panels, but some companies looking to maximize package assembly efficiencies are fabricating panels as large as 600 mm square.

Silicon-based interposer fabrication requires a rather specialized and complex sequence of processes that begin with via-hole formation. Although laser ablation can be adopted for forming the micro-via holes, the process most commonly employed for volume applications uses a deep reactive-ion etching (DRIE) process (often referred to as the “Bosch” process). This methodology can provide very small hole diameters that range between 5–20 microns. In preparation for conductor forming and via filling, a seed layer of copper or tungsten is applied to enable electroplating the additional copper required to complete the via-fill operation. Further pattern imaging and plating processes are engaged to provide interconnect features on the outer surfaces of the silicon substrate.

Glass Interposer Base Material
Significantly less costly than silicon, glass panels are being supplied by several companies specializing in manufacturing a physically durable glass with properties suitable for fan-out and/or fan-in package applications. The nominal CTE of the metalized glass panel is also a very close match to the silicon die (3 ppm/°C).

Glass is available in panel thicknesses that range from 50 μm to ≥700 μm, and the process differs significantly from silicon wafers because it will not require back grinding and polishing prior to via ablation and plating operations. The via-hole forming processes for glass include laser and electrostatic discharge as well as mechanical drilling using micro-sandblasting. Metallization on glass begins with a vapor deposition (PVD) process of copper or silver ink deposition to furnish the base for filling vias and interconnect circuitry.

High Tg, Low CTE Organic Base Material
One of the more promising materials for the high-density organic package substrate applications is promoted as an ultra-low CTE organic glass reinforced bismaleimide triazine (BT) based laminate.

While many organic dielectric materials have traditionally proven suitable for a broad range of wire-bond package applications, several leading suppliers have developed a more advanced laminate material that closely matches the very low thermal coefficient of expansion (CTE) of the silicon die element, as well as meeting the fine-line interconnect challenge for new generations of high I/O face-down mounted semiconductors. The manufacturer promises that the laminate will provide a more stable platform for mounting silicon-based semiconductor elements.

The design guidelines furnished in Table 1 relate to copper alloy via filling and conductor formation for the three base material candidates for panel-level semiconductor packaging. The geometries furnished were developed from research by the author and consensus among several colleagues involved in the technology.

The data shown may not reflect the capability of all suppliers in their respective categories, but supplier companies will generally furnish the designer with alternative design guidance related to their material sets and specific process capabilities. The supplier-developed interposer design guidelines will generally reflect factors derived from their experience, ensuring that they will likely furnish a reliable product with a high degree of quality and process yield.

Key Planning Issues for Panel Level Packaging
Assembly process methodologies will vary a great deal. Issues that will need to be resolved prior to beginning the development process include:

  • Availability of semiconductors prepared for face-down mounting
  • Establishing reliable sources for semiconductor elements
  • Specifying physical and environmental operating conditions
  • Defining package design constraints and process protocols
  • Stipulating electrical test method and post assembly inspection criteria

Semiconductor packaging methodology will continue to evolve, and market analysts project a steady growth in semiconductor package applications.

There is presently a global effort by members of SEMI (Semiconductor Equipment and Materials International) to develop standards for manufacturing panel-level packaging. The standards have already established panel size variations, thickness, as well as surface topography and panel warpage limitations.

IPC is currently in the formation stage to develop a standard guidance document for an organic-based panel format that is defined as “a wiring structure produced with a printed circuit board fabrication process that provides the final electrical interface between microelectronic devices and the underlying circuit structure.” Printed circuit manufacturing process characteristics include the use of square or rectangular panels with build-up circuit layers applied to both sides of the base using organic dielectric materials.

This column originally appeared in the February 2021 issue of Design007 Magazine.



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