Designers Notebook: Ultra High-Density Circuit Board Design

To facilitate new generations of high I/O semiconductor packaging, circuit board technology is undergoing significant refinement in both fabrication process methods and base materials selected. Many of the new high-function semiconductor package families require significantly more terminals than their predecessors. Interconnecting these very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing.

When defining the complexity level for the HDI circuit, the designer will first establish a criterion for fabricating the circuit board. This will include the board outline, thickness limitation, and any special features required for the end product. A clear objective will be established to identify the maximum number of circuit layers that are to be dedicated to signal routing and the number of layers reserved for power and ground distribution. Establishing the required number of signal layers will be determined by the overall component density and interconnect complexity.

Interconnect Capacity Analysis
This analysis is based on the board’s usable area. To determine the basic component area, the designer will first compile the mechanical outline specifications and electrical data for both active and passive components. Minimum clearances for assembly processing and in-process inspection must be considered as well as the spacing reserved for surface circuit interconnect. From this data, the designer can assign the associated land pattern geometries and the pad-stack pre-established in the CAD systems library. For those components without existing pad-stack data, the manufacturer’s mechanical and electrical data must be collected to enable the creation of new parts in the systems library.

While a significant number of semiconductor packages will have a moderate level of complexity (I/O and terminal pitch), others may have an excessively high I/O density. When assessing the PCB design complexity, first consider the component area to board area ratio. For example, the “standard” level of complexity will represent what the individual fabricators recommend for the highest yield and most favorable unit quality. When component density and area reserved for interconnect exceed the space defined by the circuit board outline and established maximum layer count, designers will need to migrate to a higher level of fabrication technology. The interconnect complexity may necessitate more circuit layers or an increase in interconnect density. Two fabrication methods can be applied when the surface area for component interface is restricted: adding additional layers to the core or base structure (increasing overall board thickness) or adopting sequential build-up (SBU) PCB fabrication.

Advances in Circuit Fabrication Capability
Printed circuit board fabrication process capabilities have continued to expand on a global scale. Fabrication process capability from one supplier to another, however, is not likely to be equal. This is because of the continuous advancement in related chemistries, processing systems, materials, and overall process control. Ensuring the success of the end-product functionality requires an understanding of the selected fabricator’s primary capability attributes and how greater design complexity will affect the PCB producibility and cost. To ensure a successful outcome for the HDI circuit board, it is important that the designer recognize the manufacturing process complexities and associated cost impact when implementing more advanced fabrication procedures.

While a majority of the components will require a relatively moderate circuit interconnect density, the high I/O array-configured components will pose the most challenging aspect of the circuit routing process. Narrow conductors routed in parallel will generally have a conductor separation that is equal to the conductors’ width. The spacing separating the circuit conductors must also consider the established minimum electrical clearance required for fabrication process variables, solder-mask adhesion, land pattern features, via land patterns, and other fixed elements on the board.

One answer for solving conductor routing roadblocks is to adopt blind via-in-land techniques to transfer a majority of the interconnect responsibility to the circuit boards’ sub-surface layers. Adapting blind and buried microvias and furnishing pre-defined routing channels will best facilitate efficient routing of these often very fine-pitch and array terminal configured semiconductor packages. When establishing copper conductor width and spacing of the circuit, the IPC-2226, for example, defines three HDI complexity levels for both external and internal locations. A relatively few companies can produce Cu conductors as narrow as 25 μm (~0.001") but they likely rely on using dielectric materials that have a very thin Cu foil or use base materials prepared for a semi-additive Cu plating process. When conductor lines and spaces must be reduced further, the fabricator will utilize base materials prepared for a semi-additive or primed for a fully additive copper plating process. Examples shown in Table 1 compare general process capability for subtractive, semi-additive, and fully additive copper deposition and micro-via hole-forming variations.

Vern_Oct_Table1_cap.jpg
Electrical interconnect on internal layers for the board enables significantly greater circuit routing density. The circuit path between key components can be more direct as well, providing greater circuit speed and lower resistance. To ensure the greatest interconnect efficiency, the designer should alternate the overall direction of the circuit path from one layer to another, using plated via holes to accommodate direction change as needed. With the circuit width and space requirement already established in the CAD system, the auto router function can quickly complete the initial interconnect process. Exhibited in Table 2 are three levels of HDI PCB conductor routing complexities.

Vern_Oct_Table2_cap.jpgHigh-Density Circuit Fabrication Solutions 

For many applications, the cost of high-density printed circuit boards has remained a detractor. Although PCB complexity has increased, the prices for HDI have declined and analysts expect this trend to continue to decline further each year. This is due in part to increased competitive conditions, but we can also attribute the trend to diligence in refining fabrication process control methods and controlling material utilization. The examples in Figure 1 compare circuit escape routing capability for very-fine-pitch BGA.

Vern_Oct_Fig1_cap.jpg
Process refinement for the ultra high-density circuit includes more efficient imaging capability and greater utilization of alternative hole-forming techniques, advances in etching and plating chemistry, and refinement in base materials and lamination methods. A key contributor to enabling higher density circuits is in the advances made in imaging. Laser direct imaging (LDI) and diode imaging systems have become mainstream technology for a wide segment of the PCB fabrication industry. Where circuit pattern imaging relied on first photoplotting the circuit pattern onto film-based masters and using contact printing to transfer the image to the etch resist coating on the copper-clad panel surface, fabricators have streamlined their processes with transferring the image directly from the CAD file onto the panel’s resist coating. Direct imaging eliminates the effect of contact film stability and improves layer-to-layer registration capability.

Before committing to adopting any level of UHDI technology, however, the designer should take the time to consult with the designated PCB supplier(s) selected to validate their capability to furnish the required complexity level at the expected production quantity. Many users have already established a business relationship with key pre-qualified suppliers that have demonstrated their level of expertise and proficiency. These suppliers can be the designer’s best source for evaluating the design before manufacturing, often suggesting refinements that will affect both cost and reliability of the finished product.

Note: The feature size dimensions furnished in the above tables may be beyond the process capability of many printed circuit board fabricators. To minimize production delays, review the selected fabricators’ design rules before initiating the HDI or UHDI project.

This column originally appeared in the October 2022 issue of Design007 Magazine.

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2022

Designers Notebook: Ultra High-Density Circuit Board Design

11-03-2022

To facilitate new generations of high I/O semiconductor packaging, circuit board technology is undergoing significant refinement in both fabrication process methods and base materials selected. Many of the new high-function semiconductor package families require significantly more terminals than their predecessors. Interconnecting these very fine-pitch, high I/O semiconductors can dramatically affect the procedures used in both circuit board design and assembly processing.

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Designers Notebook: Design for Test, Part 3

05-04-2022

The general trend in electronics is to improve performance and minimize product size, often leading to more complex printed circuit board and higher component density. Semiconductor packaging in particular, have become more complex, many having multiple functions interconnected within the package or onto the silicon itself. For products with very high component density companies soon realize that 100% test-probe access may not be possible.

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Designers Notebook: Design for Test, Part 2

03-08-2022

Current generations for PCB designs have increased in complexity. The product developer and assembly service provider, whether in-house or outsourced, must consider manufacturing efficiency, throughput, and process yield. While design for manufacturing is an absolute necessity for controlling manufacturing costs, design to accommodate product testing does need attention as well. The primary concern is to ensure that the end product will perform reliably without compromise.

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Designers Notebook: A Lesson on Automated Optical Shaping

03-07-2022

IPC APEX EXPO show and conference was safely back in full swing after skipping 2021. Because my primary interest is printed circuit board and assembly processing, I ventured onto the show floor to review some of systems exhibited that have evolved that may contribute to process efficiency and end product quality. A key benefit of attending a show like this one is that the board and assembly manufactures can view and compare similar product offerings in one place.

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Designer's Notebook: Design for Test, Part 1

02-03-2022

Circuit board fabricators remind us that multilayer boards will predictably have more components necessitating greater circuit routing complexities than that experienced on earlier applications. Also, with each generation of semiconductors it seems that the terminal count increases and the spacing between terminals shrinks, requiring designers to employ conductor lines and spaces that are far narrower than previously considered the norm.

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2021

Designers Notebook: Embedding Resistor Elements—Part 2

06-15-2021

As an alternative to the thick-film resistor process detailed in Part 1, a significant number of PCB fabricators are offering embedded thin-film resistor capability. Read Part 2 here.

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Designers Notebook: The 'New and Growing' Embedded Resistors

04-19-2021

Why is embedded resistor technology considered to be “new” and “growing” despite decades of history? In fact, a broad number of established PCB fabricators are knowledgeable about the materials and processes for embedding resistor elements but not all may be prepared to alter procedures established for their more conventional multilayer circuit board customer base.

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Designers Notebook: Developing Panel Level Semiconductor Packaging

02-22-2021

While semiconductor packaging has traditionally utilized a narrow strip of organic copper-clad organic-based laminate and wire-bond processing for the single-die BGA. Companies furnishing devices for high-volume markets are now implementing very fine-pitch alloy bumped flip-chip package technologies that enable face-down interface.

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2020

Designers Notebook: Panel-level Semiconductor Package Design Challenges

05-15-2020

Semiconductor package specialists continually work to improve high-volume manufacturing process efficiencies while reducing manufacturing costs. A majority of the commercial semiconductors are built-up on the surface of a circular-shaped silicon wafer with metalized terminal features at their perimeter to accommodate wire-bond interface with a lead-frame or package substrate. Vern Solberg explains.

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Designers Notebook: Design Challenges for Developing High-density 2.5D Interposers, Part 2

01-29-2020

In Part 2 of his column series on design challenges for high-density 2.5D interposers, Vern Solberg discusses primary base materials for 2.5D interposer applications, design guidelines, technical challenges, and key planning issues.

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Designers Notebook: PCB Design and HD Semiconductor Packaging

01-15-2020

To better meet their performance and miniaturization goals, manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. Vern Solberg covers how this and more impact PCB design and HD semiconductor packaging.

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2019

Designers Notebook: Focus of Interest at SMTAI 2019—Low-temperature Solder

10-03-2019

Both suppliers and users of solder materials participated in discussions at SMTAI 2019 related to low-temperature solder (LTS). The solder supply companies present had a wide range of material compositions that employed elements of bismuth or indium to reduce the liquidus temperature of the alloy during the joining process. Key issues that user companies are concerned with are the lower-temperature alloys selected must be reliable and exhibit shear strength, creep resistance, and resistance to thermal fatigue for the duration of the product’s life cycle.

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Designers Notebook: Embedding Components, Part 7—Semiconductor Placement and Termination Methodologies

03-11-2019

Progress in developing high-density embedded-component substrate capability has accelerated through the cooperation and joint development programs between many government and industry organizations and technical universities. In addition to these joint development programs, several independent laboratories and package assembly service providers have developed a number of proprietary processes for embedding the uncased semiconductor elements.

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Embedding Components, Part 6: Preparation for Active Semiconductor Elements

01-10-2019

Designers are well aware that a shorter circuit path between the individual die elements, the greater the signal transmission speed, which significantly reduces inductance. By embedding the semiconductors on an inner layer directly in line with related semiconductor packages mounted on the outer surface, the conductor interface distance between die elements will be minimized.

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2018

Embedding Components, Part 5: Alternative Termination Methodologies and Surface Plating Variations

12-19-2018

Because they are furnished with a very thin profile, resistor and capacitor components with different values can be mounted directly onto land patterns on a subsurface layer of the printed circuit structure. However, handling and placing of these small components requires systems with a high level of positional accuracy. Interconnection can be accomplished using either deposited solder paste and reflow processing or applying a conductive polymer material. Due to the extremely small land pattern geometries required for mounting the miniature passive components, companies commonly rely on precision dispensing these materials.

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Embedding Components, Part 4: Passive Component Selection and Land Pattern Development

11-29-2018

As noted in Part 3 of this series, a broad range of discrete passive component elements are candidates for embedding, but the decision to embed these component elements within the multilayer circuit structure must be made early in the design process. While many of these components are easy candidates for integrating into the substrate, others may not be suitable, or they are difficult to rationalize because they involve more complex process methodology.

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Embedding Components, Part 3: Implementing Discrete Passive Devices

11-15-2018

Most of the passive components used in electronics are discrete surface mount components configured to mount onto land patterns furnished on the surface of a PC board. Designers have several choices for providing passive functions in a system design, such as discrete surface-mounted passives, array passives or passive networks, integrated (Rs and Cs) passive devices, and embedded discrete passive components.

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Designers Notebook: Strategies for High-Density PCBs

01-01-2018

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as HDI processing. The primary driver for HDI is the increased complexity of the more advanced semiconductor package technology. These differences can be greater than one order of magnitude in interconnection density.

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2017

Strategies for High-Density PCBs

11-27-2017

As hand-held and portable electronic products and their circuit boards continue to shrink in size, the designer is faced with solving the physical differences between traditional printed board fabrication and what’s commonly referred to as high-density interconnect (HDI) processing.

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Embedding Components, Part 2

07-30-2017

Technology and processes for embedding capacitor and inductor elements rely on several unique methodologies. Regarding providing capacitor functions, IPC-4821 defines two methodologies for forming capacitor elements within the PCB structure: laminate-based (copper-dielectric-copper) or planar process and non-laminate process using deposited dielectric materials.

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Embedding Components, Part 1

06-30-2017

The printed circuit has traditionally served as the platform for mounting and interconnecting active and passive components on the outer surfaces. Companies attempting to improve functionality and minimize space are now considering embedding a broad range of these components within the circuit structure. Both uncased active and passive component elements are candidates for embedding but the decision to embed components within the multilayer circuit structure must be made early in the design process.

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2016

Specifying Lead-Free Compatible Surface Finish and Coating for Solderability and Surface Protection

07-06-2016

A majority of the components furnished for electronic assembly are designed for solder attachment to metalized land patterns specifically designed for each device type. Providing a solder process-compatible surface finish on these land patterns is vital...

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Flexible and Rigid-Flex Circuit Design Principles, Part 6

05-26-2016

The designer is generally under pressure to release the documentation and get the flexible circuit into production. There is, however, a great deal at risk. Setting up for medium-to-high volume manufacturing requires significant physical and monetary resources. To avoid potential heat from management, the designer must insist on prototyping the product and a thorough design review prior to release.

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Flexible and Rigid-Flex Circuit Design Principles, Part 5

04-27-2016

The outline profile of the flexible circuit is seldom uniform. One of the primary advantages of the flexible design is that the outline can be sculpted to fit into very oblique shapes. In this column, Vern Solberg focuses on outline planning, physical reinforcement, and accommodating bends and folds in flexible and rigid-flex circuits.

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Flexible and Rigid-Flex Circuit Design Principles, Part 4

03-30-2016

All of the design rules for the glass reinforced-portion of the board (land pattern geometry for mounting surface mount devices, solder mask and the like) are now well-established. One unique facet of fabricating the rigid-flex product is how the flexible portion of the circuit is incorporated with the rigid portion of the circuit. As a general rule for multilayer PCB design, furnish a balanced structure by building up the circuit layers in pairs (4, 6, 8 and so on).

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Flexible and Rigid-Flex Circuit Design Principles, Part 3

03-02-2016

This column focuses on methods for specifying base materials, and also address copper foil variations and fabrication documentation. It is important to research the various products in order to choose the one that best meets the design requirements.

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Flex and Rigid-Flex Circuit Design Principles, Part 2

02-19-2016

Flexible circuits are commonly developed to replace ordinary printed circuit board assemblies that rely on connectors and hardwire for interconnect.

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Flex and Rigid-Flex Circuit Design Principles, Part 1

01-27-2016

Flexible circuits represent an advanced approach to total electronics packaging, typically occupying a niche that replaces ordinary printed circuit board assemblies and the hard-wire interface needed to join assemblies.

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2005

PCB Designers Notebook: Flexible Circuit Design

01-03-2005

The flexible circuit was originally used as a conductive element for interfacing signals from one electronics assembly to another.

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