Obsessing over Conductor Surface Roughness: What’s the Effect on Dk?

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017 in Santa Clara, California.

For those of you who know me, you know that I have been researching practical methods to model conductor surface roughness and its effect on insertion loss (IL). I have presented several papers on the subject over the last couple of years. It’s one of my pet projects. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

Everyone involved in the design and manufacture of PCBs knows that one of the most important properties of the dielectric material is the relative permittivity (εr), commonly referred to as dielectric constant (Dk). But in reality, Dk is not constant at all. It varies over frequency as you will see later.

We often assume the value reported in manufacturers’ data sheets is the intrinsic property of the material. But in actual fact, it is the effective dielectric constant (Dkeff) generated by a specific test method. When you compare simulation against measurements, you will often see a discrepancy in Dkeff and IL, due to the increased phase delay caused by surface roughness. This has always bothered me. For a long time, I was always looking for ways to come up with Dkeff from data sheet numbers alone. Thus the obsession and motivation for my recent research work.

Since phase delay, also known as time delay (TD), is proportional to Dkeff of the material, my theory was that the surface roughness profile decreases the effective separation between parallel plates, thereby increasing the electric field (e-field) strength, resulting in additional capacitance, which accounts for an increase in effective Dk and TD.

To read this column, which appeared in the March 2017 issue of The PCB Design Magazine, click here.

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2017

Obsessing over Conductor Surface Roughness: What’s the Effect on Dk?

04-12-2017

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

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2016

The PDN Bandini Mountain and Other Things I Didn’t Know I Didn’t Know

03-30-2016

Originally, Bandini Mountain referred to a mound of fertilizer built by the Bandini Fertilizer Company in California prior to the 1984 Los Angeles Olympics. When the company went bankrupt, this mound of fertilizer was left behind. Steve Weir coined this term to describe the large resonant frequency peak formed by the parallel combination of the on-die capacitance and the package lead inductance, as seen from the die looking into the PDN.

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2014

Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

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Bert's Practical Design Notes: Accelerating the SI Learning Curve - Bogatin's SI Academy

08-06-2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

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2013

Are Guard Traces Worth It?

08-14-2013

Some claim that a guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor's signal. But others believe separating the victim trace to at least three times the line width from the aggressor is good enough. Bert Simonovich addresses both arguments.

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Bert's Practical Design Notes: Are Guard Traces Worth It?

08-14-2013

Some claim that a guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor's signal. But others believe separating the victim trace to at least three times the line width from the aggressor is good enough. Bert Simonovich addresses both arguments.

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2012

Bert's Practical Design Notes: Perils of Lumped Via Modeling

05-30-2012

Popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I'll show you why it is no longer appropriate to think this way.

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Bert's Practical Design Notes: The "Stubinator" vs. Back-Drilling

04-11-2012

I was intrigued by a DesignCon 2010 paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSvia, and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call this technology the "Stubinator."

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Backplane High-Level Design: The Secret to Success

01-04-2012

In my previous column, I touched briefly on the concept of backplane high-level design (HLD). For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts in an organized manner, and later provides the roadmap to follow for detailed design of the backplane. This week, I will touch on key aspects that go into this process.

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2011

Bert's Practical Design Notes: Why Backplane Architecture is Crucial

11-04-2011

I am often asked what I do for a living. When I say high-speed signal integrity and backplane architect, the next question is usually, "What is a backplane architect?" By my definition, a backplane architect is any person who plans, devises or contrives the achievement of a backplane design. And the earlier you consider the backplane's physical architecture, the more successful the project will be.

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Bert's Practical Design Notes: Fiber Weave-Induced Timing Skew

09-17-2011

A couple of times this year, fiber weave effect timing skew came up for discussion on the SI-List that many of us subscribe to. This is becoming more of an issue for many designers as bit rates continue to soar upwards. For signaling rates of 5GB/s and beyond, it can actually ruin your day. So what is fiber weave effect anyway, and why should we be concerned about it?

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Bert's Practical Design Notes: Cross-Sectional Geometries

08-10-2011

So, why do we need to study PCB cross-sectional geometries? Because they describe the details of the dielectric substrates, traces and reference planes in a PCB stackup. Their relationship to each other is used to predict the characteristic impedance and interaction of the respective traces. Understanding these geometries can help you determine odd-mode and even-mode impedance, average and differential impedance, crosstalk and more.

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Practical Differential Via Modeling Made Easy

07-14-2011

In my last column, I discussed the twin-rod model. Now I'll explain how a twin-rod transmission line model can be the basis for a practical differential via circuit modeling technique and a simple alternative to a 3D field solver. This method can yield an approximation much faster than a field solver, and when you need a rough estimate, this via modeling method may be just what you need!

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The Three Amigos: Twin-Rod, Rod-Over-Plane and Coax

06-22-2011

In almost all cases, equations used to calculate the loop inductance and capacitance of transmission lines are approximations. However, there are three unique cross-sectional geometries that have exact equations: Twin-rod, rod-over-plane and coaxial. I've dubbed them "The Three Amigos." Get to know them -- they can be your friends.

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IBIS Output Impedance Made Easy

05-03-2011

I subscribe to the SI-List forum on signal integrity. People often pose the question, "How do you find the driver impedance information from the IBIS file?" Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path. Let's look into IBIS output impedance.

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New Column: Bert's Practical Design Notes

04-13-2011

Over the years, I have held a variety of hardware design engineering positions and pioneered several advanced technologies into products. After all this time as an engineer, I still have the passion I had as kid to learn and understand new things. This column is about sharing some of that passion.

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