Simulators are very convenient for getting quick answers without lengthy, expensive, and time-consuming measurements. Simulators range from simple spreadsheet-based illustration tools^{[1]} to very sophisticated 3D field solvers^{[2]}. Somewhere in the middle, we have the generic circuit simulators—the most well-known among them being SPICE. Berkeley SPICE has been the grand-daddy of all SPICE tools^{[3]}, and these days, there are many professional SPICE variants available. These tools have been around for a long time, and we usually take the validity of their output for granted. While the tools may be bug-free, no tool can give us perfect answers for just any arbitrary numerical input; sometimes, we can be surprised if we forget about the numerical limits and the limitations imposed by internal default values.

As an example, I will show a few simulation results on a simple ladder-like power distribution network, all done with the free LTspice simulator ^{[4]} from Linear Technologies, now part of Analog Devices.

Figure 1: LTspice schematics of a simple PDN.

Figure 1 shows the schematic diagram of a simplified ladder model of a point-of-load power distribution network (PDN). The PDN is represented by four cascaded blocks. On the left is an ideal voltage source with series resistance and inductance modeling the DC source. To its right is a PI model of the PCB with plane resistance and inductance, as well as bulk and ceramic capacitors.

The next block describes the package with its series resistance, inductance, and capacitance. The 10-µF capacitance value suggests that this is not only the static capacitance of the package planes, but it also represents package capacitors. The last block on the right describes the die with a series RL term, a parallel capacitance, and a parallel load resistance, which is determined by the nominal voltage and the average power consumption.

Outside of these blocks is a 1A AC current source injecting test current into the silicon node. Since all elements are linear and time-invariant models, the actual current value does not matter, but the 1A value is convenient because the simulated V (load) output voltage directly gives us impedance without the need for further scaling.

Figure 2: Impedance magnitude and phase of the simple PDN shown in Figure 1.

Figure 2 shows the result. The heavier line is the impedance magnitude with its scale on the left, the phase is the thin line with its scale on the right. We see four resonance peaks and one sharp dip on the plot. Peaks 1, 2, and 3 come from the anti-resonances of neighboring capacitor banks. For instance, the first peak is formed by Lsrc and Cbulk, and the LC parallel resonance of the 100-nH and 10000-µF values produce the 5-kHz resonance peak. To find the second peak, which comes from the series inductance of the Cbulk capacitor and the capacitance of Cceramic, we need to know the assumed inductance of Cbulk.

You will notice that there are no series resistance and inductance symbols in series to the capacitors, so does it mean the simulation assumes zero values for those parasitics? In this regard, LTspice is unique among the SPICE circuit simulators. We can specify the usual simple parasitics without adding the corresponding schematic elements.

Figure 3: Screenshot explaining the capacitor equivalent circuit in LTspice.

The equivalent circuit, as defined in LT Wiki^{[5]}, is shown in Figure 3. We can specify not only the equivalent series resistance and inductance but also two parallel loss elements and a body capacitance. These parameters will be frequency-independent entries. But how do we enter these parameters if we don’t want to type up the SPICE deck manually?

Figure 4: Options to enter parasitic values for capacitors in LTspice.

LTspice makes it easy, offering multiple options. In Figure 4, the left portion shows what happens if we move the cursor over a capacitor in the schematic diagram and right-click. A window pops up where we can manually enter various attributes. On the right, you see the window which pops up when you hold the control key while you right-click. The two windows offer somewhat different choices. On the left—in addition to the equivalent series resistance, inductance, and body capacitance—we have only one parallel resistance entry. On the right, we can enter every parameter listed in Figure 3, including the initial condition, temperature, and the multiplier (m or x), which is a convenient way to simplify the schematics if we have m number of identical capacitors connected in parallel. We can also hide parameters or make them visible on the schematic using the checkmark in the last column. For the schematics shown, I turned on the feature only for the capacitance value; otherwise, the view would become very crowded. Notice that I show the actual parasitic values that were used to generate figure 2. Now, we see that the series inductance of the bulk capacitor is 10 nH, and this creates the anti-resonance with the 100-µF ceramic capacitor. From these two values, we get a 150-kHz antiresonance frequency, and that is exactly where Peak 2 is. Peak 3 is at 150 MHz, and it appears to be split by the sharp and deep Notch 4.

Table 1: Parasitic values of capacitors that were used to generate Figure 2.

Table 1 summarizes the capacitor-parasitic values for all four capacitors. We may wonder if the values in this table represent reality because ESR and ESL for the ceramic capacitor appear to be unrealistically low. Yes, it would be unrealistic to expect these values from a single capacitor, but if we imagine that these values represent ten pieces of 10-µF ceramic capacitor with 5-mOhm ESR and 1-nH ESL in each, then it looks reasonable.

If we move on to look at the resonance at Peak 3, we realize that it is formed by the 10-nF Cdie capacitance and the equivalent inductance of the entire network looking back from the silicon, which is the well-known die-package resonance. By the time we properly add up all series and parallel inductances, it comes out around 160 pH. The antiresonance with the 10-nF Cdie value comes out close to 100 MHz, where the split antiresonance peak happens.

Figure 5: Impedance magnitude and phase of the simple PDN showed in Figure 1, but all parallel body capacitance is set to zero.

We still need to understand where the two extra resonances—Notch 4 and Peak 5—come from. To get the answer, we need to go back to Figure 4 and check what happens with the parameters that we did not fill out. On the left, there are two parameters we left empty: parallel capacitance and parallel resistance. What happens if we explicitly set the body capacitance to zero? The result is shown in Figure 5. Notch 4 and Peak 5 disappeared, but the rest remained practically unchanged.

Figure 6: Equivalent circuit of inductor parasitics and attribute list.

Now, the resonance pattern makes sense, but there is still something happening. Why do we have 5-mOhm impedance at low frequencies, when the circuit calls out only 1 mOhm and three times 0.1-mOhm resistor values in the series path, altogether 1.3-mOhm series resistance? We need to look at the definitions of the inductors. The definition of inductor attributes is shown in Figure 6^{[5]}.

Figure 7: Parasitic definitions of the Lsrc inductor.

In the same way we did it for the capacitors, we can call up the parameter-entry windows for the inductors as well. In Figure 7, we see two parasitic components listed: series resistance and parallel capacitance. We also see a note at the bottom of the left window. There is a 1-mOhm default value for the series resistance. This means if we do not make an entry there, the tool will automatically add a 1-mOhm value (but this automatically-added value does not show up in the series resistance input field). This explains the low-frequency value in Figure 2 since we have four series inductors, each will have 1-mOhm series resistance by default.

Figure 8: Impedance magnitude and phase of the simple PDN showed in Figure 1, with forcing zero body capacitance of capacitors and zero series resistance of inductors.

If we explicitly call out zero for the series resistance parasitics on all inductors, we get Figure 8. Now, the low-frequency value starts at the correct 1.3-mOhm value, but we can also notice that the first two peaks get a little bigger. This is happening because we removed the extra series resistances, which helped to lower the antiresonance peaks. Note that with the circuit values used in this example, explicitly calling out zero body capacitance for the inductors will not change the result.

This is eventually what we expect: a smooth impedance profile, no unexpected and unexplained sharp resonances, and asymptotic low-frequency impedance matches the sum of series resistance values.

Figure 9: Checking the body capacitance default value for the capacitor model.

We are almost done, but it still would be useful to check the capacitor’s equivalent circuit one more time and take another look at the body capacitance. To make it simple, we look at a single capacitor, as shown in Figure 9. We set the main capacitance as a parameter so that we can step it and set the ESR and ESL to fixed values—10 mOhm and 1 nH, respectively. To see what happens, we intentionally do not specify the parallel body capacitance; the entry is left blank.

We step the capacitance from 1 pF to 1F in four large logarithmic steps and sweep the frequency from 1 mHz to 1 THz. The result shows that, in fact, a parallel body capacitance is added by the simulator, but its value is not fixed; it depends on the other parameters. With the values used here, the body capacitance seems to be approximately one million times smaller than the main capacitance. While this looks like a huge ratio (and it is), we see that if we simulate our circuit over many decades of frequencies, this small default body capacitance value still can cause unexpected artifacts. The good news is that it is easy to deal with; we just have to remember to call out specifically zero body capacitance, unless, of course, when we know its correct value and want to simulate the effect of the body capacitance.

And a final note: Remember that all numerical tools have to set limits for the input numbers they can accept and process, whether the tools will tell you and remind you. Next time, when you see unexpected things in circuit-simulation results, first make sure that the input numbers, including potential defaults, are set correctly.

References

1. Parallel Impedance of Four Groups of Capacitors.

2. High-Frequency Structure Simulator.

3. Berkeley SPICE.

4. LTspice.

5. LTwiki.

This column originally appeared in the August 2020 issue of *Design007 Magazine.*