The Bare (Board) Truth: 5 Questions About Improving Thermal Management

In this column, I will focus on answering five questions about thermal management at the design and PCB levels. These questions were sent to me from one of the owners at Monsoon Solutions, where I now work. Jeff Reinhold, EE and designer, asked: 

  1. When I get a datasheet that calls out some area of copper for heat dissipation, how do I translate that requirement to fit my board that may or may not have the specified area available?
  2. How much heat does a via dissipate, and how does size and fill change that?
  3. Does moving heat to internal layers help at all or even work?
  4. How do I identify potential thermal issues?
  5. How do I translate a heat dissipation requirement, in whatever form it is given, into parameters I can use to design a solution?

Some of the questions I can answer from my “previous life” in PCB fabrication, but for others, I asked my co-workers for their comments.

Kevin_Carrington.jpgQuestion #1
Regarding the first question, Kevin Carrington, a design engineer at Monsoon, said:
Thermal management is all about deltas. Heat only moves along a gradient, so if heat isn’t actively being removed, then it’s simply spread, which means your delta-T is diminished. Spreading over a long enough time achieves steady-state, so understanding a use scenario is often important. Putting more copper in the circuit board would have zero impact on thermal management if the board is at a steady-state condition. 

The physical size of parts is very important when considering heat dissipation. A great example is the power SO-8 package that many discrete FETs come in nowadays and have largely replaced the DPAK components. Parts in those packages are often rated very similarly for operating parameters, but the DPAK is far superior when it comes to getting heat out because of the size of the thermal tab.

Accounting for the resistance change of metal with temperature can have a big impact on the system. If you ignore copper—like the circuit board, big common-mode chokes, or inductors—you might be cutting a lot of power dissipation and heat out of your analysis. Even if you include them but use room-temperature copper calculations, there can be big differences between analysis and reality. Thermal foam can be a very useful way to get heat to a metal case when a closed system is used (e.g., no fan). It’s critical to have the foam in compression, otherwise, it won’t achieve the desired low thermal resistance.

The ambient temperature is very important, and “ambient” is often not considered properly. Just because the air outside your product is 50°C doesn’t mean inside is 50°C. For most electronics, the actual ambient temperature in which they’re operating is the steady-state temperature inside the enclosure.

Question #2
For the most part, the most effective way of getting the heat out/dissipating heat from one side to the other is to use filled vias. 

The best filled-via is a stitching via with solid copper plug matching the CTE of the copper being used on the PCB. The next best solution would be copper epoxy-filled vias. After that, a silver-filled via works okay. Lastly, epoxy fill can get some of the heat out. All work better than a standard stitching via that is unfilled. Air—particularly stagnant air—is a poor thermal conductor, so any material filling the via will lower that thermal pathway’s resistance.

A smaller via filled with solid copper and many such stitching vias in an array would be the best if using vias to dissipate heat. Also, note that many fabricators have a size limitation on the size of filled vias; most say 0.008”–0.020.”

Question #3
Generally, not increasing the copper area via a ground or power plane and even adding higher copper weight internally is not the answer. This approach may be quite beneficial for transient thermal excursions, but for most products, steady-state power dissipation is the concern. Here, I would recommend a basic analysis through rough equations would be of a greater benefit than adding copper layers internally. But, as Kevin said, producing a prototype that can be tested in a thermal chamber would really tell you where you are.
 
If you are looking to dissipate heat and are considering adding copper, the best layers would be the outer layers with copper pour. This helps EMI but can dissipate heat through the surface. Again, as Kevin said, “There is no magic copper layer that will be the best way to get the heat out.”
 
Regarding heat in an enclosure, what is the best way to get the heat out when a board is in an enclosure? The first and oldest way is to simply have a fan in the enclosure.Not being able to do that, Kevin mentioned a trick he learned when he was designing for DVRs that cannot have a fan. Another good method is to utilize compressed foam in the enclosure, but why compressed? Common sense would say uncompressed foam is porous. The idea behind the foam is primarily spreading the heat to a chassis or other system component, which can hopefully get the heat out. The compression helps achieve lower thermal resistance, improving the effectiveness of the thermal pathway.

Question #4
A simple operating test in a thermal chamber using a prototype design can help make substantial leaps in understanding product risks, missed aspects of analysis, and correlating calculations.

Question #5
Question #5 is probably the best and toughest question to answer. The short version is to use the aforementioned techniques to identify, mitigate, evaluate, and optimize the thermal operating conditions of your product. Often, this means implementing a somewhat blind first attempt, using the best practices you can within your constraints, and then checking whether the performance is adequate. Drawing upon previous experience is a key part of this, whether that’s the capability of a device, heat sink, or enclosure or understanding the environment in which it operates.

In general, thermal management is something of an iterative process, and explicit technical requirements aren’t available nor knowable. For example, the most common requirement is related to the electronic components on the board not exceeding their rated junction temperatures. How to do that is a combination of the system implementation operating in the field conditions, which usually requires prototyping or simulation to baseline. Knowing that a part will dissipate 3W of power is simply not enough. Once you have an idea of where you’re at, then you can assess opportunities for improvement.

Generally, these optimizations involve:

  • Lower the power dissipation of the device (component selection, functional operating load)
  • Improve the heat transfer conditions (thermal pathways through PCB, heat sinks, etc.)
  • Constrain the operating environment/use case (software-controlled limits, environmental ratings)

Whenever something is a risk, we must mitigate it, and because the nature of thermal management is heavily influenced by environmental conditions, prototyping is key. Even if it’s just a small portion of the system, being able to characterize the limits will enable an understanding of whether simple thermal pathway improvements can succeed or whether drastic architecture changes are required. The latter is quite important to know as soon as possible. Lastly, use thermal vias and heat sinks where possible.

To remove the heat created by power dissipation of the components, and especially the power components, one solution is to improve the vertical heat transfer through the supporting material.

Typically, this is achieved by providing thermal through-contacts, or thermal vias, going through the substrate from the top side to the bottom side. It is typical to use thermal vias beneath the rear contact or mounting surfaces of the components and particularly the power components, and then plate the through-holes through the entire thickness of the material/substrate.

A second remedy for the heat dissipation problem relates to external heat removal. For this, the substrate may be mounted on a metallic cooling body or heat sink, such as a copper plate, which conveys the power dissipation heat to a cooling system. Such a cooling body may be separated from the supporting substrate by an electrical insulating layer, such as an insulating film or foil. After applying the components to the mounting surface of the substrate, the components are electrically connected with contact surfaces or specifically contact pads and the traces.

To achieve this, a solder paste is printed onto the contact surfaces and the top surface of the thermal vias and is then melted in a reflow soldering process to solder-connect the components.

Conclusion
I hope this column has helped to explain just a few ways to stay out of the hot seat. And, as always, I appreciate any feedback. I can be reached at markt@msoon.com.
 
This column originally appeared in the September 2020 issue of Design007 Magazine.

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2020

The Bare (Board) Truth: 5 Questions About Improving Thermal Management

09-10-2020

Mark Thompson from Monsoon Solutions answers five questions about thermal management at the design and PCB levels, including how much heat a via dissipates, how to identify potential thermal issues, and more.

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The Bare (Board) Truth: ‘The Want of a Nail’ and the Butterfly Effect

02-17-2020

After exploring the Todd Rundgren song "The Want of a Nail" and the butterfly effect, Mark Thompson explains how small changes in design characteristics that happen at a PCB fabrication level can have larger consequences for the final product.

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2019

The Bare (Board) Truth: Teaching the Next Generation—An Overview of Today’s University Courses

09-05-2019

In this column, Mark Thompson focuses on the University of Washington, where he counted approximately 163 programs in their catalog of electronics courses. He shares the top 19 courses he thinks are the most valuable for emerging electronic engineers if he were to start his electronics career over again.

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The Bare (Board) Truth: Fabrication Starts With Solid Design Practices

06-20-2019

It’s a fact: Great board design is the key to a great PCB. I’m even more certain of this after spending two days in a wonderful class presented by Rick Hartley titled “Control of Noise, EMI, and Signal Integrity in High-speed Circuits and PCBs.” Several times during Rick’s presentation, I wanted to slap myself in the forehead and say, “I should have had a V-8!”

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Board Negotiations: Design Rules and Tolerances

06-03-2019

Here are several examples of how a PCB fabricator can deal with various tolerances. Let’s look at “press fit” applications for tool sizes. Typically, a given plated hole or slot is ±0.003” and a typical non-plated hole or slot is ±0.002”. So, what does the fabricator do when a plated hole is called out as ±0.002”? The simple answer is to calculate how much plating there will be in the hole barrel, and then over-drill to accommodate the ±0.002 tolerance.

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The Bare (Board) Truth: Eliminate Confusion

03-18-2019

This column will address eliminating confusion that creates remakes both from the end-user/designer and the fabrication house. Let’s say you’ve asked for a material type on your drawing that is not either readily available or used by your fabricator. Here, you should expect the fabrication house to respond quickly and have all the deviations at once for you to review. This includes any impedance width changes, material types, or copper weights to produce the part. Any deviations regarding drawing notes such as wrap plate requirements that cannot be incorporated due to insufficient space or the extra etch compensation to meet the wrap plate requirement should also be addressed.

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2018

The Bare (Board) Truth: Getting on the Same Page—A Data Story

11-26-2018

Thickness callouts for single-sided or double-sided orders are even more critical. As a fabricator, we can control the thickness of the multilayer by using different combinations of prepregs/cores. If a customer calls out a single-sided or double-sided job as 0.008”, is this the core dielectric or an overall dielectric? If 0.008” represents the core dielectric callout on a 2-ounce finished part, the final thickness would be closer to 0.013”. If the callout for 0.008” pertains to the overall finished thickness, we would need to start at a 0.004” core to finish at approximately 0.009” after plate, surface finish, and mask.

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The Bare (Board) Truth: Refining Output Data Packages for Fabricators

05-02-2018

One of the biggest issues PCB fabricators face is the completeness (or incompleteness) of the data output package we receive from customers on a new PCB. In this column, I am going to present what is needed, from a fabricator’s perspective, for a good output package and why.

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2016

The Bare (Board) Truth: Hey, They’re Just Vias—or Are They?

11-28-2016

I get this phone call once a week: “Mark, what is the smallest mechanical via that can be done by your company?” I reply, “What will the tolerance for the vias in question be?” If they say, “Oh, your standard +/-.003” tolerances,” I must tell them the min via would be around .0078” with a signal pad of at least .014” and an anti-pad of at least .018”. What if they don't have that kind of room?

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The Top 10 Ways Designers Can Increase Profits

04-19-2016

Can you truly increase profitability through PCB design practices? Mark Thompson believes you can. And it starts with a philosophy that embraces DFM techniques. Then you must be ready for the initial release to a fabricator by ensuring that you are communicating all of your specifications and needs clearly to the fabrication house so that you get an accurate quote. Let’s dive in, starting with Number 10 and working our way to the most important way a designer can increase company profits.

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2015

The Do’s and Don’ts of Signal Routing for Controlled Impedance

06-10-2015

In this column, we will once again be focusing on controlled impedance structures, both from the layout side and the simulation side. I will break them down into the sub-categories of the models they represent and the important points to remember when using the various models. I will also be asking questions such as, “Why would a fabricator ask for a larger impedance tolerance?” and “Where does the fabricator draw the line for controlling various structures?”

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The Bare (Board) Truth: Tips for Getting the Boards You Need

05-22-2015

This column is about meeting each customer's needs. Some customers' requirements are as simple as a specific definition for a fiducial size, rail tooling, or orientation feature, while other customers may require special processes. Mark Thompson offers fabricator tips that can help designers get the boards they need.

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What Will 2015 Bring?

02-25-2015

I’ve been thinking over what 2015 might look like, from my point of view at a PCB fabrication company. Let me first start out with some broad overviews of trends from 2014 that I see continuing. On my end, I certainly expect to see more RF work, more hybrid analog-digital PCBs, and more surface finishes for lead-free assemblies. And that’s just the tip of the iceberg.

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2014

Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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The Bare (Board) Truth: Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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2013

Qualifying Your Fabricator: Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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The Bare (Board) Truth: Qualifying Your Fabricator - Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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A PCB Design Potpourri

10-16-2013

In this column, Mark Thompson revisits topics covered in some of his previous columns and fleshes them out with new, updated information. Thompson says, "In this job, I truly learn something every day, and I'm happy to share a few notable nuggets with you."

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2012

The Bare (Board) Truth: I'm From CAM and I'm Here to Help

12-12-2012

In this column, Mark Thompson shows that fabricators are not necessarily meddling in your design; some of them really do want to help make your board right the first time. And he also demonstrates how patience and perseverance can go a long way with a customer!

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The Bare (Board) Truth: Tales From the Fab Shop

05-16-2012

Designers continue to create the same-net spacing violations when relying on autorouters. Surface features connected elsewhere on an internal plane may have copper pour too close to other metal features. Electrically it doesn't matter whether these features bridge, but for most fabricators, any sliver thinner than 0.003" has the potential to flake off and redeposit elsewhere. By Mark Thompson.

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Design to Fab: Making it Work

03-30-2012

A very large customer sent us two 4-layer boards riddled with differential pairs, with no information about any controlled impedances or specific dielectrics. When we asked if these were to be controlled, the customer was most appreciative and realized that some mention of the impedances, threshold and tolerance should have been made initially. When in doubt, talk to the customer!

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Mark Thompson: IPC APEX EXPO Wrap-Up

03-07-2012

It was a mostly sunny week in San Diego, where IPC APEX EXPO returned after a long absence. I thought the San Diego Convention Center was a great choice for a venue. And this year, the engineers and designers on the show floor were looking at new processes and technologies like kids in a candy store.

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2011

The Bare (Board) Truth: Slow Down and do it Right

09-21-2011

You may be tempted to cut corners in an effort to stay on schedule. But cutting corners to save time does not save anything if it results in a new rev. Let's talk about the risks associated with assuming your board house will find and be able to correct errors in your designs. You'll avoid most of these if you slow down and do it right!

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The Bare (Board) Truth: Four Common Fabrication Questions

08-03-2011

A few months ago, I covered the "10 Most Common Fab Misconceptions." In this column, I will take a similar approach and address four of the most common fabrication questions that I hear. These same questions keep popping up, over and over. But I believe I can dispel the myths surrounding these challenges, and explain their solutions.

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The Bare (Board) Truth: Scene and Heard at IPC APEX EXPO

06-01-2011

I'm always amazed at the diversity of people I see while people-watching in Vegas. And this year, we saw a great diversity of new products and processes at APEX. Some were new combinations of older technologies, while others addressed problems in a completely new, different way.

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2010

The Bare (Board) Truth: Netlist Mismatches Redux

12-01-2010

Let's start by clarifying the intent of the netlist compare. I still get requests to just "generate a netlist" based on the customer's Gerbers. As I have said, since the intent of a netlist compare is to compare the design criteria against the exported Gerber files, this would never find a mismatch.

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RoHS for Fabricators and Designers: Fact and Fiction

11-03-2010

Most of you have heard of the European Union's RoHS directive. Some people mistakenly think it's mainly an assembly problem. But how, exactly, does RoHS pertain to PCB fabricators and designers? Is RoHS-compliant the same as RoHS-compatible?

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Timing is Everything in Controlled Impedance Fabrication

07-20-2010

According to Mark Thompson, timing can make or break your controlled impedance board. With many jobs going through turnkey environments, late communication about impedance issues takes valuable time out of the fabrication process and can delay delivery of product, leaving the end-user and the turnkey assembler unhappy.

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The Bare (Board) Truth: How to Qualify Your Fabricator

06-16-2010

This column is written from the viewpoint of you, the customer. What should you look for when qualifying a fabricator? Sure, you want the company to be IPC Class 3 6012 capable and ISO-certified, and you may need them to be ITAR-certified as well. But what other criteria can help you separate the wheat from the chaff, so to speak?

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Impedance Lines: Keep Them on the Inside

03-02-2010

Keeping those impedance-controlled lines on the inside layers of a circuit board is a great idea for a number of reasons. Let's start with the facts: You'll make your fabricator and your customer very happy by remembering to keep them on the inside.

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2009

More CAM Edits Revealed!

11-24-2009

A typical CAM department makes numerous edits prior to fabrication. Today, I will elaborate on inner-layer feature CAM edits, including the addition of flow and starburst patterns and constraints for scored jobs, as well as the process for fabricating edge-plated features.

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The Bare (Board) Truth: What Happens to Your CAM Files?

07-22-2009

What does the CAM department do to your files and what does that mean to you? The following is a brief synopsis of the edits that are likely to be performed at CAM prior to fabrication.

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The Bare (Board) Truth: Basic Impedance Fab Guidelines, Part 1

06-10-2009

When we talk about signal integrity or impedance lines, there are some very basic guidelines to follow. Remember, impedance mismatches cause signal reflections, which reduce voltage and timing margins.

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