The Bare (Board) Truth: Via Basics

This month’s column will address what vias are and what they are used for, as well as how they are used in PCB design. I’ll also cover some criteria on pad size vs. via size for fabrication.

Introduction to Vias
But first, how did vias come about? That’s easy. The first PCBs were all through-hole components, meaning a plated hole from one side to the other, from top to bottom. When board densities became more of an issue based on available real estate, components went from a 4-pin to an 8-pin or a 12-pin connector, etc., using all through-holes to a surface-mount-type connector in an effort to use less board space. Thus, the first use of mechanical through-hole vias.

The process for this is quite simple. Based on the tolerance expressed on the drill drawing, the vias (and component through-holes) are drilled larger (typically, 0.004–0.005”) than the necessary finished hole size. If the part is a simple two-layer board, the process is as follows. The dielectric material is pulled then taken to the drilling department. Before this operation, the CAM department will specify the proper drill size to use, and a drill programmer will set up the start and stop codes using those drill sizes for the N/C drill machine.

Once drilled, the part would go through a series of cleaners and conditioners and then into a catalyst before the electroless copper stage, where the electroless copper deposition is done. The electroless stage is not an electrowinning process like electroplate and only lays down about 0.4 mils of electroless copper in the barrel of the hole and on the panel surface. This acts as a “tooth” or a bit of metal for the electroplated copper to adhere to.

The parts are then taken to an imaging department where a photoresist is applied to the panels, and the panels are imaged. Then, the image is developed and taken to the electroplating department where the now-exposed traces and pads are plated—hence the reason holes are compensated larger before the plating process. After plating, they end up at the size and within the tolerance described on the fabrication drawing.

A multilayer is slightly different. The core material is pulled and coated in the dry-film department, and the parts are also imaged. If a standard multilayer with no blind or buried vias exists (I will get into them later in this column), the process in the plating department is a develop, etch, and strip process. The image is a negative image, so where the light sees the panel, it hardens the resist, thus protecting the traces and plane layers.

IPC Standards
Why did I talk about how a fabricator processes a given hole? Let’s talk about IPC standards. However, I will not talk about Class 1 since most products are Class 2, 3, or even 3A.

In a Class 2 IPC-6012 part, both external and internal holes can have as much as 90-degree breakout and still be acceptable (Figure 1). But for Class 3 and Class 3A, the external must have a minimum of a 0.002” annular ring after drill and plate, and the internal layers must have at least 0.001” annular ring.

That means if the part needs to meet a higher class based on its function and application, you need to design the board knowing the fabricator will over-drill the plated holes approximately 0.004–0.005” over the hole’s size stated on the drill/fab drawing. A 0.008” hole with a 0.012” pad would not be acceptable, as the part will be over-drilled by 0.004–0.005”; in the case of Class 3 and Class 3A, the part must also have an additional 0.002” annular ring. Add to this that a fabricator has both a true position tolerance and a machine tolerance (normally ±0.003”), so truthfully, given Class 3 IPC-6012, the pad size should take into consideration all of these variables. Is that even feasible?

Thompson_Fig1_1120.jpg

 Figure 1: IPC annular ring acceptance criteria.

Let’s say the Class 3 IPC-6012 via size is 0.008” expressed as ±0.003” tolerance. If that were true, you would need to drill the hole at approximately 0.0138”, and the machine tolerance plus the true hole position tolerance of ±0.003” would mean a 0.016–0.018” addition to the nominal hole size (again expressed as ±0.003”). Thus, the pad size would need to be 0.026”. That is not feasible in board design where real estate/board area issues exist.

This brings me to the reason I bring up the fabrication process for holes in the first place. If the holes are simply vias, for many years now, I have told our customers (in my previous life as a board fabrication guy) to call them out as ±0.003” the entire hole size. This way, a 0.008” via could be drilled at 0.008”, and no compensation or over-drill would be required. This now means a Class 3 IPC-6012 part could be as little as 0.016–0.018” for a pad size and even less if negotiated with the fabricator if they have good control of their machine and true position tolerance.

One thing I was told many years ago was, if we added up all the tolerances, we would never be able to build a PCB. Luckily, many of the tolerances cancel out each other.

Teardrops
What about the use of teardrops? Teardrops are simply a fillet at the junction where the trace connects to the pad. This is done so that the hole will not break out of the throat where the trace meets the pad causing a disconnect. If you have enough room on your board design, one way to mitigate the induced drill wander that occurs in a fab environment is to use teardrops. Some examples of various teardrop styles are shown in Figure 2.

Thompson_Fig2_1120.jpg

Figure 2: Snowman teardrop (for obvious reasons) on the left; fillet-style teardrop on the right.

Via Types
Here, I’ll detail a variety of via types, including (1) through-hole vias, (2) blind vias, (3) buried vias, and (4) stacked and staggered vias (Figure 3).

thompson_fig3_1120.jpg1. Through-Hole Vias
These are simply vias that go from the top to the bottom layer and are through-hole plated. They are used to pass a signal from one side of the board to the other or to make interconnects in the case of a multilayer.

2. Blind Vias
These are vias that either start from the top or the bottom side and terminate on a given internal layer. They are typically used for where board space is a premium. Examples include blinds 1–2, blinds 1–5, and blinds 3–6 (6 being the bottom layer). Note that you will need a separate NC drill file for each blind via scenario.

This can typically be done 2–3 times, but normally no more than 2–3 times from a given side. The limitation is the number of plating cycles the outer layer sees. A 10-layer example would look like top to layer 2, top to layer 3, top to layer 4, bottom layer to layer 9, bottom layer to layer 8, and bottom layer to layer 7. To make more layer connections for 14-, 16-, or 18-layer boards, buried vias can be used in conjunction with the blind vias.

Types of Blind Vias

Sequential Blind Vias
The termination inner layer is processed on the core, leaving the associated outer layer as a copper sheet only to be imaged after lamination.

Controlled-Depth or Back-Drilled Vias
All the inners are processed as a normal multilayer and then laminated as normal. The connection to the inner blind layer is done with controlled-depth mechanical drilling. The drilling can drill partially into the core between layers but must not connect to the layer past the blind termination layer.

Laser Blind Microvias
Use of a laser, either Nd:YAG (neodymium-doped yttrium-aluminum-garnet) or Nd:YLF (yttrium-lithium-fluorine), can only go through very thin substrates. An infrared laser can inherently penetrate deeper but is not able to remove copper with the longer wavelength they emit.

Laser Microvias
These are typically used for high-density interconnection (HDI) designs. Due to the physical shape of a laser microvia, the depth of a given microvia is typically two or less consecutive layers deep due to the copper plating constraints of having to remove the ablated ash produced by the laser. They can be stacked or staggered, and both are additive processes. Microvias are used for higher functionality in less space, such as cellphones or tablets.

3. Buried Vias
A via is either mechanically or laser drilled between inner layers and does not extend to the surface layers (such as blind vias). They are drilled and filled (either laser or mechanically drilled). They are usually filled during the lamination process by the prepreg.

Uses of Various Vias

Via-in-Pad and VIPPO
With the extensive use of fine-pitch devices and smaller PCBs came the advent of via-in-pad structures. Via-in-pad is literally a via inside of a pad. It is first drilled, plated, or flash plated, filled with either epoxy or copper epoxy, and planarized so the surface is made flat for the assembly process. The advantage of this technology is tighter, more closely packed component placement, enhanced thermal management, and elimination of parasitic inductance and capacitance as these reduce the signal path lengths.

Via-in-pad plated over (VIPPO) is basically the same as via-in-pad with the exception that it is associated with an SMT pad, not a normal pad, such as one for a blind via. Additionally, VIPPO is also used where they will also back-drill (controlled depth drill) out the excess metal from the hole beneath the termination to an internal layer.

Thermal Vias
These dissipate heat from one side of the board to the opposite side of the board and are typically placed directly below (or as close as possible) heating elements or components that generate a lot of heat. PCBs are more conductive across the board than they are through the dielectric.

If traces are only present on the outer layers, then most of the heat is carried sideways (horizontally), and the internal core planes may be cooler. This adds thermal stitching vias connecting surface features to the internal planes and creates more conductivity that dissipates heat to the core, reducing the overall temperatures more effectively.

Stitching Vias
Via stitching uses ground coupling. The most common use for stitching vias in a plane is to ensure short return paths for signals or to help maintain a constant ground. As soon as any current starts to flow, it will cause a voltage across the copper through which it is flowing, serving to both spread the current out but also cause the ground to bounce around. Via stitching can be an effective and low-effort way to more tightly couple ground across the PCB.

Shielding Vias or Via Fences
After reading a lot of literature on shielding vias, I will paraphrase the information I found. Via fences, also known as “picket fences,” are structures to improve isolation between components that would otherwise be coupled by electromagnetic fields. They contain a row or two, or even three rows, of vias spaced close enough together to form an electromagnetic wave barrier.

Via fences can be used to shield microstrip and stripline transmission lines or functional circuits from each other. However, via fences too close to the line being guarded can degrade the isolation of the line/circuit. They can also be used around the periphery of a board to prevent electromagnetic interference with other equipment.

4. Stacked and Staggered Vias
Stacked and staggered microvias are done with a laser (Nd:YAG or Nd:YLF) exactly as described earlier. Stacked vias are literally stacked upon each other by an additive process, and staggered vias are staggered so that they do not reside directly over each other.

The advantage of stacking vias is extremely dense board designs, such as via-in-pad structures within tight-pitch BGA footprints. For this, the vias are drilled with a laser and then plated, filled, and planarized to create the interconnect. The next layer is done by laminating another layer on top of the previous via. This can typically be done 3–4 times (or more, depending upon the fabricator). Then, the surface layer is planarized (made flat) so that the PCB is flat at assembly, and no “part rocking” will occur.

Conclusion
In this column, I repeatedly oversimplified both the function and process for vias. Ultimately, consult your chosen fabricator for more detail on capabilities and process limitations. Thanks for reading!

Mark Thompson, CID+, is a senior PCB technologist at Monsoon Solutions Inc. To read past columns or contact Thompson, click here. Thompson is also the author of The Printed Circuit Designer's Guide to… Producing the Perfect Data Package. Visit I-007eBooks.com to download this book and other free, educational titles.

This column originally appeared in the November 2020 issue of Design007 Magazine.

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2020

The Bare (Board) Truth: Via Basics

11-13-2020

In this month’s column, Mark Thompson addresses what vias are and what they are used for, as well as how they are used in PCB design. He also covers some criteria on pad size vs. via size for fabrication and how vias came about.

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The Bare (Board) Truth: 5 Questions About Improving Thermal Management

09-10-2020

Mark Thompson from Monsoon Solutions answers five questions about thermal management at the design and PCB levels, including how much heat a via dissipates, how to identify potential thermal issues, and more.

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The Bare (Board) Truth: ‘The Want of a Nail’ and the Butterfly Effect

02-17-2020

After exploring the Todd Rundgren song "The Want of a Nail" and the butterfly effect, Mark Thompson explains how small changes in design characteristics that happen at a PCB fabrication level can have larger consequences for the final product.

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2019

The Bare (Board) Truth: Teaching the Next Generation—An Overview of Today’s University Courses

09-05-2019

In this column, Mark Thompson focuses on the University of Washington, where he counted approximately 163 programs in their catalog of electronics courses. He shares the top 19 courses he thinks are the most valuable for emerging electronic engineers if he were to start his electronics career over again.

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The Bare (Board) Truth: Fabrication Starts With Solid Design Practices

06-20-2019

It’s a fact: Great board design is the key to a great PCB. I’m even more certain of this after spending two days in a wonderful class presented by Rick Hartley titled “Control of Noise, EMI, and Signal Integrity in High-speed Circuits and PCBs.” Several times during Rick’s presentation, I wanted to slap myself in the forehead and say, “I should have had a V-8!”

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Board Negotiations: Design Rules and Tolerances

06-03-2019

Here are several examples of how a PCB fabricator can deal with various tolerances. Let’s look at “press fit” applications for tool sizes. Typically, a given plated hole or slot is ±0.003” and a typical non-plated hole or slot is ±0.002”. So, what does the fabricator do when a plated hole is called out as ±0.002”? The simple answer is to calculate how much plating there will be in the hole barrel, and then over-drill to accommodate the ±0.002 tolerance.

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The Bare (Board) Truth: Eliminate Confusion

03-18-2019

This column will address eliminating confusion that creates remakes both from the end-user/designer and the fabrication house. Let’s say you’ve asked for a material type on your drawing that is not either readily available or used by your fabricator. Here, you should expect the fabrication house to respond quickly and have all the deviations at once for you to review. This includes any impedance width changes, material types, or copper weights to produce the part. Any deviations regarding drawing notes such as wrap plate requirements that cannot be incorporated due to insufficient space or the extra etch compensation to meet the wrap plate requirement should also be addressed.

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2018

The Bare (Board) Truth: Getting on the Same Page—A Data Story

11-26-2018

Thickness callouts for single-sided or double-sided orders are even more critical. As a fabricator, we can control the thickness of the multilayer by using different combinations of prepregs/cores. If a customer calls out a single-sided or double-sided job as 0.008”, is this the core dielectric or an overall dielectric? If 0.008” represents the core dielectric callout on a 2-ounce finished part, the final thickness would be closer to 0.013”. If the callout for 0.008” pertains to the overall finished thickness, we would need to start at a 0.004” core to finish at approximately 0.009” after plate, surface finish, and mask.

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The Bare (Board) Truth: Refining Output Data Packages for Fabricators

05-02-2018

One of the biggest issues PCB fabricators face is the completeness (or incompleteness) of the data output package we receive from customers on a new PCB. In this column, I am going to present what is needed, from a fabricator’s perspective, for a good output package and why.

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2016

The Bare (Board) Truth: Hey, They’re Just Vias—or Are They?

11-28-2016

I get this phone call once a week: “Mark, what is the smallest mechanical via that can be done by your company?” I reply, “What will the tolerance for the vias in question be?” If they say, “Oh, your standard +/-.003” tolerances,” I must tell them the min via would be around .0078” with a signal pad of at least .014” and an anti-pad of at least .018”. What if they don't have that kind of room?

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The Top 10 Ways Designers Can Increase Profits

04-19-2016

Can you truly increase profitability through PCB design practices? Mark Thompson believes you can. And it starts with a philosophy that embraces DFM techniques. Then you must be ready for the initial release to a fabricator by ensuring that you are communicating all of your specifications and needs clearly to the fabrication house so that you get an accurate quote. Let’s dive in, starting with Number 10 and working our way to the most important way a designer can increase company profits.

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2015

The Do’s and Don’ts of Signal Routing for Controlled Impedance

06-10-2015

In this column, we will once again be focusing on controlled impedance structures, both from the layout side and the simulation side. I will break them down into the sub-categories of the models they represent and the important points to remember when using the various models. I will also be asking questions such as, “Why would a fabricator ask for a larger impedance tolerance?” and “Where does the fabricator draw the line for controlling various structures?”

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The Bare (Board) Truth: Tips for Getting the Boards You Need

05-22-2015

This column is about meeting each customer's needs. Some customers' requirements are as simple as a specific definition for a fiducial size, rail tooling, or orientation feature, while other customers may require special processes. Mark Thompson offers fabricator tips that can help designers get the boards they need.

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What Will 2015 Bring?

02-25-2015

I’ve been thinking over what 2015 might look like, from my point of view at a PCB fabrication company. Let me first start out with some broad overviews of trends from 2014 that I see continuing. On my end, I certainly expect to see more RF work, more hybrid analog-digital PCBs, and more surface finishes for lead-free assemblies. And that’s just the tip of the iceberg.

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2014

Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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The Bare (Board) Truth: Understanding the Typical CAM Process

03-19-2014

Not all board fabricators have the ability to have both CAD and CAM. You may say to yourself, "But a CAM tool should be able to do some, if not all, CAD functions," and that is true; but if you are really getting to the design level, you need to have a design team.

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2013

Qualifying Your Fabricator: Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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The Bare (Board) Truth: Qualifying Your Fabricator - Identifying Winners (and Losers)

12-24-2013

Columnist Mark Thompson writes, "Based on today's board complexities, a review should be done prior to quote to make sure no manufacturing issues occur. This is critical when it comes to things like minimum pre-preg interfaces on high-copper coil boards or jobs with unique reference planes for various impedance scenarios."

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A PCB Design Potpourri

10-16-2013

In this column, Mark Thompson revisits topics covered in some of his previous columns and fleshes them out with new, updated information. Thompson says, "In this job, I truly learn something every day, and I'm happy to share a few notable nuggets with you."

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2012

The Bare (Board) Truth: I'm From CAM and I'm Here to Help

12-12-2012

In this column, Mark Thompson shows that fabricators are not necessarily meddling in your design; some of them really do want to help make your board right the first time. And he also demonstrates how patience and perseverance can go a long way with a customer!

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The Bare (Board) Truth: Tales From the Fab Shop

05-16-2012

Designers continue to create the same-net spacing violations when relying on autorouters. Surface features connected elsewhere on an internal plane may have copper pour too close to other metal features. Electrically it doesn't matter whether these features bridge, but for most fabricators, any sliver thinner than 0.003" has the potential to flake off and redeposit elsewhere. By Mark Thompson.

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Design to Fab: Making it Work

03-30-2012

A very large customer sent us two 4-layer boards riddled with differential pairs, with no information about any controlled impedances or specific dielectrics. When we asked if these were to be controlled, the customer was most appreciative and realized that some mention of the impedances, threshold and tolerance should have been made initially. When in doubt, talk to the customer!

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Mark Thompson: IPC APEX EXPO Wrap-Up

03-07-2012

It was a mostly sunny week in San Diego, where IPC APEX EXPO returned after a long absence. I thought the San Diego Convention Center was a great choice for a venue. And this year, the engineers and designers on the show floor were looking at new processes and technologies like kids in a candy store.

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2011

The Bare (Board) Truth: Slow Down and do it Right

09-21-2011

You may be tempted to cut corners in an effort to stay on schedule. But cutting corners to save time does not save anything if it results in a new rev. Let's talk about the risks associated with assuming your board house will find and be able to correct errors in your designs. You'll avoid most of these if you slow down and do it right!

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The Bare (Board) Truth: Four Common Fabrication Questions

08-03-2011

A few months ago, I covered the "10 Most Common Fab Misconceptions." In this column, I will take a similar approach and address four of the most common fabrication questions that I hear. These same questions keep popping up, over and over. But I believe I can dispel the myths surrounding these challenges, and explain their solutions.

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The Bare (Board) Truth: Scene and Heard at IPC APEX EXPO

06-01-2011

I'm always amazed at the diversity of people I see while people-watching in Vegas. And this year, we saw a great diversity of new products and processes at APEX. Some were new combinations of older technologies, while others addressed problems in a completely new, different way.

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2010

The Bare (Board) Truth: Netlist Mismatches Redux

12-01-2010

Let's start by clarifying the intent of the netlist compare. I still get requests to just "generate a netlist" based on the customer's Gerbers. As I have said, since the intent of a netlist compare is to compare the design criteria against the exported Gerber files, this would never find a mismatch.

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RoHS for Fabricators and Designers: Fact and Fiction

11-03-2010

Most of you have heard of the European Union's RoHS directive. Some people mistakenly think it's mainly an assembly problem. But how, exactly, does RoHS pertain to PCB fabricators and designers? Is RoHS-compliant the same as RoHS-compatible?

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Timing is Everything in Controlled Impedance Fabrication

07-20-2010

According to Mark Thompson, timing can make or break your controlled impedance board. With many jobs going through turnkey environments, late communication about impedance issues takes valuable time out of the fabrication process and can delay delivery of product, leaving the end-user and the turnkey assembler unhappy.

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The Bare (Board) Truth: How to Qualify Your Fabricator

06-16-2010

This column is written from the viewpoint of you, the customer. What should you look for when qualifying a fabricator? Sure, you want the company to be IPC Class 3 6012 capable and ISO-certified, and you may need them to be ITAR-certified as well. But what other criteria can help you separate the wheat from the chaff, so to speak?

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Impedance Lines: Keep Them on the Inside

03-02-2010

Keeping those impedance-controlled lines on the inside layers of a circuit board is a great idea for a number of reasons. Let's start with the facts: You'll make your fabricator and your customer very happy by remembering to keep them on the inside.

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2009

More CAM Edits Revealed!

11-24-2009

A typical CAM department makes numerous edits prior to fabrication. Today, I will elaborate on inner-layer feature CAM edits, including the addition of flow and starburst patterns and constraints for scored jobs, as well as the process for fabricating edge-plated features.

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The Bare (Board) Truth: What Happens to Your CAM Files?

07-22-2009

What does the CAM department do to your files and what does that mean to you? The following is a brief synopsis of the edits that are likely to be performed at CAM prior to fabrication.

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The Bare (Board) Truth: Basic Impedance Fab Guidelines, Part 1

06-10-2009

When we talk about signal integrity or impedance lines, there are some very basic guidelines to follow. Remember, impedance mismatches cause signal reflections, which reduce voltage and timing margins.

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