New SI Techniques for Large System Performance Tuning

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Large systems with multiple configuration options and extended product lifecycles provide performance tuning opportunities such as SerDes setting optimizations and manufacturing improvements. This paper describes newly-developed techniques for equalization tuning and discontinuity reduction, offering additional design margin. Cost reductions are also achieved as new signal integrity (SI) techniques demonstrate performance parity, removing non-essential re-timers and PCBs layers. This is the fourth in a series of DesignCon papers detailing the design and implementation of a system characterized by multiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps).   

1. Introduction

Simulation advancements released over 10 years ago allowed examination of serial links in greater detail, identifying performance limiters which motivated further refinements in the same. Once tuned, the technologies were scaled to rapidly scan thousands of serial links to identify failure modes in rogue channels enabling their correction and confident transition into production using simulated bit error ratios (BERs) as a qualifying metric . This paper leverages and enhances these same technologies to provide large-system SerDes setting optimization and cost reduction, highlighting recent advancements in equalization optimization techniques and algorithms.

SerDes setting optimizations are applied to a wide range of channels across systems of various sizes. Optimization techniques are described, automated, applied to thousands of links and performance gains are quantified. SerDes tuning processes were simpler when one or two taps were available in the Tx and the Rx equalization options were few. However, with newer technologies the number of setting options grows exponentially as a larger number of Tx taps are available and trade-offs must be made between Tx and Rx equalization. As such, new tuning techniques are necessary. Furthermore, using re-timers to handle excessively long channels (40+ inches) seemed essential in previous generations of serial links. However as PCB and SerDes technologies continue to improve—combined with the optimization techniques described—we find that re-timers may not necessarily warrant their associated cost, complexity, and real estate.  

Manufacturing improvements that enhance performance are also described. One example of a short connection with seven discontinuities spread across multiple PCB layers that initially showed multiple impedance changes in the 25% range is demonstrated to become nearly transparent over time. Relentless measurements on bare PCB fabrications, good vendor communication, and manufacturing process improvements and controls are key. Breakout traces longer than ¼” should be compensated. However, intentional trace layout manipulation in the presence of impedance control and re-imaging during fabrication must be carefully managed.

Dual-diameter via construction is shown to be a viable solution for reducing discontinuities when via lengths exceeds 200 mils, by using simulation confirmed by lab measurement to achieve 20% channel eye improvement in channels of various lengths. SI analysis also verifies acceptable performance in reduced layer-count PCBs to achieve lower cost.

To read this entire article, which appeared in the July issue of The PCB Design Magazine, click here.



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