New SI Techniques for Large System Performance Tuning


Reading time ( words)

Abstract

Large systems with multiple configuration options and extended product lifecycles provide performance tuning opportunities such as SerDes setting optimizations and manufacturing improvements. This paper describes newly-developed techniques for equalization tuning and discontinuity reduction, offering additional design margin. Cost reductions are also achieved as new signal integrity (SI) techniques demonstrate performance parity, removing non-essential re-timers and PCBs layers. This is the fourth in a series of DesignCon papers detailing the design and implementation of a system characterized by multiple thousands of interconnected serial links spanning dozens PCBs, operating at 3rd and 4th generation serial link data rates (6 to 12 Gbps).   

1. Introduction

Simulation advancements released over 10 years ago allowed examination of serial links in greater detail, identifying performance limiters which motivated further refinements in the same. Once tuned, the technologies were scaled to rapidly scan thousands of serial links to identify failure modes in rogue channels enabling their correction and confident transition into production using simulated bit error ratios (BERs) as a qualifying metric . This paper leverages and enhances these same technologies to provide large-system SerDes setting optimization and cost reduction, highlighting recent advancements in equalization optimization techniques and algorithms.

SerDes setting optimizations are applied to a wide range of channels across systems of various sizes. Optimization techniques are described, automated, applied to thousands of links and performance gains are quantified. SerDes tuning processes were simpler when one or two taps were available in the Tx and the Rx equalization options were few. However, with newer technologies the number of setting options grows exponentially as a larger number of Tx taps are available and trade-offs must be made between Tx and Rx equalization. As such, new tuning techniques are necessary. Furthermore, using re-timers to handle excessively long channels (40+ inches) seemed essential in previous generations of serial links. However as PCB and SerDes technologies continue to improve—combined with the optimization techniques described—we find that re-timers may not necessarily warrant their associated cost, complexity, and real estate.  

Manufacturing improvements that enhance performance are also described. One example of a short connection with seven discontinuities spread across multiple PCB layers that initially showed multiple impedance changes in the 25% range is demonstrated to become nearly transparent over time. Relentless measurements on bare PCB fabrications, good vendor communication, and manufacturing process improvements and controls are key. Breakout traces longer than ¼” should be compensated. However, intentional trace layout manipulation in the presence of impedance control and re-imaging during fabrication must be carefully managed.

Dual-diameter via construction is shown to be a viable solution for reducing discontinuities when via lengths exceeds 200 mils, by using simulation confirmed by lab measurement to achieve 20% channel eye improvement in channels of various lengths. SI analysis also verifies acceptable performance in reduced layer-count PCBs to achieve lower cost.

To read this entire article, which appeared in the July issue of The PCB Design Magazine, click here.

Share

Print


Suggested Items

Effects of PCB Fiber Weave on High-Speed Signal Integrity

12/31/2018 | Chang Fei Yee, Keysight Technologies
This article studies the effect of PCB fiber weave on signal integrity in terms of mode conversion and differential channel loss due to intra-pair skew. The study used Keysight ADS 2DEM simulation to observe s-parameter (i.e., insertion loss and differential to common-mode conversion) and an eye diagram for signal transmission at 1 Gbps and 10 Gbps.

Calculation of Frequency-Dependent Effective Roughness Dielectric Parameters for Copper Foil Using Equivalent Capacitance Models

01/02/2019 | Marina Y. Koledintseva, Metamagnetics Inc.*, and Tracey Vincent, CST of America
Knowledge of the correct parameters of laminate PCB dielectrics refined from any copper foil roughness impact and the proper foil roughness characterization are important constituents of modeling high-speed digital electronics designs.

Life Beyond 10 Gbps: Localize or Fail!

11/20/2018 | Yuriy Shlepnev, Simberian
Ideally, all interconnects should look like uniform transmission lines (or wave-guiding structures) with the specified characteristic impedance. In reality, an interconnect link is typically composed of transmission lines of different types (microstrip, strip, coplanar, coaxial, etc.) and transitions between them such as vias, connectors, breakouts and so on. Transmission lines may be coupled to each other that cause crosstalk. The transitions may reflect and radiate energy due to discontinuities in signal and reference conductors. The crosstalk, reflections and radiation cause unwanted and sometime unpredictable signal degradation.



Copyright © 2019 I-Connect007. All rights reserved.