Getting Signal Integrity Right by Design

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As clock frequencies increase and active devices and interconnect traces shrink and are placed ever closer together, signal integrity (SI) becomes an increasing challenge. Today, SI is typically addressed late in the design process after the PCB layout has been completed by performing complex and time-consuming 3D extractions and simulations for high-speed lines.

But with little attention being paid to SI during the layout process, simulation frequently identifies numerous SI problems. Multiple design and simulation iterations are often required to resolve these issues, in some cases causing delays in bringing the product to market and increasing nonrecurring expenses. An embedded SI checker helps by automatically checking for common mistakes that frequently cause SI problems such as missing shielding, return path discontinuities, ground or power loops, impedance mismatches, etc. Even with this approach, simulations are still required as a final check, but reducing the number of issues that must be addressed at this late stage helps bring the product to market faster and reduces engineering costs.

SI Design Challenges

Increasing data rates, higher IO counts and greater design complexity are leading to greater challenges in meeting SI and electromagnetic interference (EMI) requirements. For instance, 3DIC technology utilizes through-silicon vias (TSVs) to eliminate bond wires and further reduce interconnection distance in stacked chip configurations, providing higher speed performance and lower power consumption at the cost of creating many new opportunities for harmful radiation. Meanwhile, regulatory authorities are tightening electromagnetic compatibility (EMC) requirements by requiring compliance at higher and higher frequencies. The trend towards integrating multiple radios—each of which is an intentional radiator—into electronic products creates further challenges.

But the complexity of today’s designs and the high levels of automation required to complete them in a reasonable time period usually prevent electrical designers from paying more than cursory attention to SI during the design process. Nearly all PCB design tools have built-in design rule checkers (DRCs) but they typically evaluate the design from a manufacturability perspective, rather than from an SI perspective. Simulation is normally performed after the design has been completed, when it becomes possible to model its performance by calculating a 3D solution of Maxwell’s equations, which provides an elegant mathematical representation of electromagnetic interactions. The result, all too often, is that large numbers of SI problems are identified at a point relatively late in the design process when changes are very expensive to make. As a general rule, the cost of design changes generally increases by an order of magnitude or more as the design moves from conceptual to detailed to simulation.

To read this entire article, which appeared in the July 2016 issue of The PCB Design Magazine, click here.


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