ICD Adds Matched Delay Optimization to Stackup Planner


Reading time ( words)

In-Circuit Design Pty Ltd (ICD), Australia, developer of the ICD Stackup and PDN Planner software, has released a Matched Delay Optimization feature for the Stackup Planner. 

Signals propagate at the speed-of-light in free space. However, this speed varies dramatically depending on the surrounding dielectric materials. Each layer, of a multilayer PCB, can have a very different propagation speed. This is particularly important for the latest high-speed DDR3/4 memory devices. The new “Matched Delay Optimization” feature, of the ICD Stackup Planner, allows you to not only match the length of busses, but takes this one step further by automatically calculating the appropriate length required to match the delay exactly. The integrated field solver simulates the flight time, of each signal layer, to quickly give you the results you need to effectively route memory.

ICD.jpg 

“A matched length of 2.3 inches for a DDR3/4 Data lane can produce up to 70ps delta, between signal layers, leaving the timing way outside the required DDR3/4 setup and hold times,” said Barry Olney, CEO. “Designers need to pay strict attention to the signal propagation, on each layer, ensuring the total flight time of the critical signals match, regardless of length. The ICD Stackup Planner now allows you to optimize this delay."

The relative signal propagation is displayed as a bar graph, once the matched length has been set. Selecting “Matched Delay” automatically optimizes the length, of each signal layer, to match the maximum delay. The user can then route the data lane, to the exact delay, in their preferred design tool.

About In-Circuit Design Pty Ltd

In-Circuit Design Pty Ltd, based in Australia, developer of the ICD Stackup and PDN Planner software, is a PCB Design Service Bureau and specialist in board level simulation. Visit www.icd.com.au.

Share

Print


Suggested Items

‘The Trouble with Tribbles’

06/17/2021 | Dana Korf, Korf Consultancy
The original Star Trek series came into my life in 1966 as I was entering sixth grade. I was fascinated by the technology being used, such as communicators and phasers, and the crazy assortment of humans and aliens in each episode. My favorite episode is “The Trouble with Tribbles,” an episode combining cute Tribbles, science, and good/bad guys—sprinkled with sarcastic humor.

IPC-2581 Revision C: Complete Build Intent for Rigid-Flex

04/30/2021 | Ed Acheson, Cadence Design Systems
With the current design transfer formats, rigid-flex designers face a hand-off conundrum. You know the situation: My rigid-flex design is done so now it is time to get this built and into the product. Reviewing the documentation reveals that there are tables to define the different stackup definitions used in the design. The cross-references for the different zones to areas of the design are all there, I think. The last time a zone definition was missed, we caused a costly mistake.

Why We Simulate

04/29/2021 | Bill Hargin, Z-zero
When Bill Hargin was cutting his teeth in high-speed PCB design some 25 years ago, speeds were slow, layer counts were low, dielectric constants and loss tangents were high, design margins were wide, copper roughness didn’t matter, and glass-weave styles didn’t matter. Dielectrics were called “FR-4” and their properties didn’t matter much. A fast PCI bus operated at just 66 MHz. Times have certainly changed.



Copyright © 2021 I-Connect007. All rights reserved.