-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Brooks' Bits: How Many Vias Does It Take To…?
May 4, 2016 | Douglas G. BrooksEstimated reading time: 2 minutes
Sounds like the opening words of a bad joke. Well, here’s the answer, and it’s no joke: One! That’s right. No matter how much current you are putting down the trace, all you need is a single via. And a small one, at that.
OK, that last statement might not be true in EVERY single case. But it is true in a LOT more cases than you think. I will explain why in this column.
During 2015, I enjoyed a very productive collaboration with Dr. Johannes Adam, from Leimen, Germany. That collaboration resulted in several papers, but one in particular is relevant for this column, “Via Currents and Temperatures.” In that paper, we used a simulation tool, thermal risk management (TRM), developed by Dr. Adam, to simulate current flowing through a via and then determine the temperature of the via. The conventional wisdom is that the conducting cross-sectional area of the via should be the same as (or greater than) the cross-sectional area of the trace (conductor.) IPC 2152 explicitly endorses this:
The cross-sectional area of a via should have at least the same cross-sectional area as the conductor or be larger than the conductor coming into it. If the via has less cross-sectional area than the conductor, then multiple vias can be used to maintain the same cross-sectional area as the conductor.
But our results contradicted this; they suggested that the temperature of the via was controlled by the trace, and as long as the trace was sized correctly, any old (single) via was good enough.
If there was ever a result that cried out “show me,” this was it.
So I set out on a path to build a test board, test it, and verify the simulation results. This type of study would not have been possible without the cooperation of several people and organizations. In particular, I want to thank my longtime partner Dave Graves (now with Monsoon Solutions in Bellevue, Washington) for helping prepare the final artwork for the test board. C-Therm Technologies (Fredericton, New Brunswick) graciously measured the thermal conductivity of the board material to facilitate the simulation. And a special thanks to Prototron Circuits of Redmond, Washington, who provided the test boards and also the microsectioning work and measurements. And my collaborator on trace thermal issues, Johannes Adam, continues to be a great help in evaluating results.
Figure 1 illustrates the relevant portion of the test board. There are two 0.5 oz. test traces, each six inches long, each consisting of two, three-inch segments (top and bottom) connected by a single 10 mil diameter via. The via is plated to approximately one ounce. One test trace is 27 mil wide, providing approximately the same cross-sectional area as the conducting area of the via. The other trace is 200 mil wide. It is important to note that the vias are identical for the two traces.
To read this entire article, which appeared in the March 2016 issue of The PCB Design Magazine, click here.
Suggested Items
Stan Rak: Elevating the Ideas and Insights of IPC's Thought Leaders Program
04/25/2024 | Stanton Rak, SF Rak CompanyAs a member of the IPC Thought Leaders Program (TLP), I am responsible for identifying knowledge-sharing opportunities that can generate ideas and insights that strengthen the IPC community as well as create a sustainable and lasting future for its members. I am delighted to highlight some of my recent contributions as a member of the TLP.
Alternative Manufacturing Inc. Awarded QML Requalification to IPC J-STD-001 and IPC-A-610
04/24/2024 | IPCIPC's Validation Services Program has awarded an IPC J-STD-001 and IPC-A-610 Qualified Manufacturers Listing (QML) requalification to Alternative Manufacturing Inc (AMI).
IPC Design Competition Champion Crowned at IPC APEX EXPO 2024
04/24/2024 | IPCAt IPC APEX EXPO 2024 in Anaheim, California, five competitors squared off to determine who was the best of the best at PCB design.
Big Win for Defense Production Act Budget Allocation in FY24 Budget
04/23/2024 | I-Connect007 Editorial TeamOne year ago, President Biden issued a determination that chips and packaging are critical for national security. Since that time, much work has been done to continue the conversation in Washington, elevating the importance of the entire chips value chain, and including printed circuit boards and substrates, without which chips cannot operate.
Real Time with... IPC APEX EXPO 2024: A Conversation with IPC's CEO: New Venue, Sustainability, and More
04/23/2024 | Real Time with...IPC APEX EXPOBarry Matties hosts Dr. John W. Mitchell, CEO of IPC, on the final day of IPC APEX EXPO 2024. They discuss the new venue in Anaheim and broach a range of topics, from traffic and booth experiences to workforce development, sustainability, and the CHIPS Act. And they offer advice for newcomers as IPC looks forward to an even better show experience next year.