Routing DDR3 Memory and CPU Fanout

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DDR3 memory is so pervasive, it’s almost inevitable that professional PCB designers will use it. This article advises how to properly fanout and route DDR3 interfaces, even in very high-density and tightly packed board designs.

DDR3 Design Rules and Signal GroupsEverything starts with the recommended high-speed design rules for routing DDR3 in groups. During DDR3 layout, the interface is split into the command group, the control group, the address group, as well as data banks 0/1/2/3/4/5/6/7, clocks, and others. It’s recommended that all the signals belonging to the same group be routed “the same way;” i.e., using the same topology and layer transitions.Figure 1: All signals in the DATA 6 group are routed “the same way,” using the same topology and layer transitions.As an example, consider the routing sequence shown in Figure 1. All the DATA 6 group signals go from layer 1 to layer 10, then to layer 11, and after that to layer 12. Every signal within the group makes the same layer transitions and generally takes on the same routing distance and topology.One of the advantages of routing the signals this way is that during length tuning (a.k.a. delay or phase tuning), the Z-axis length in the vias can be ignored. This is because all the signals routed “the same way” will have exactly the same via transitions and lengths through vias. (You can be more liberal with vias as long as their lengths are taken into consideration for length matching).Creating DDR3 GroupsThe first step before routing is to create the necessary signal groups, which can be done from the project’s schematic. The specific method for doing this will depend on how constraints are managed in the software, but nets that are constrained and grouped will follow certain rules during routing. Read the full article here.Editor's Note: This article originally appeared in the June 2014 issue of The PCB Design Magazine.


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