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Today the geometries of board-level circuits are being driven to optimize space, cost, and performance, resulting in a large selection of fine-pitch components, connectors, and integrated circuits. Overcoming the challenges and the complexities of the circuit is challenging enough without considering the obstacles of mass producing the end-product with extremely high yield expectations.
Improperly defined PCB footprints are the culprits behind thousands of costly, time-consuming failure analysis investigations. For the sake of simplicity, it will be assumed that the circuit and all connections are schematically correct and any failures are the result of unreliable footprint designs assembled properly onto the PCB. The most common failures are caused by solder shorts or open circuits that develop during assembly. Other potential defects include poorly contemplated pin escape routing, improper thermal design, and the dreaded intermittent failure.
It is imperative to implement PCB layouts with a strong understanding of the assembly process and how the PCB component footprint can influence yield and performance. This is especially important today, due to factors such as: (a) the expansion of integrated circuit product lines manufactured with pin pitches specified at 0.4 mm and below, and (b) the plethora of package variations available, such as chip scale packages (CSP) and quad flat packages (QFN) in double and single rows.
Prior to addressing footprint design techniques, we must define some layer definitions used in PCB manufacturing, and explain how these layers impact the final board. The pin will be identified as the actual solder contact point that is used to mechanically and electrically connect the package to the PCB. Once the PCB has been etched, laminated, and the vias have been electroplated according to design, the next process step involves solder mask application to the outer surfaces of the PCB using printers, photo-masking, and radiation hardening. The role of the solder mask is to keep the solder on the pin during reflow. The solder paste is applied during assembly and is controlled by a layer called the paste mask. Read the full article here.Editor's Note: This article originally appeared in the March 2014 issue of The PCB Design Magazine.