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A Small Leak can Sink a Great Ship: EMC Behavior of Traces Crossing Split Planes, Part I
July 3, 2013 |Estimated reading time: 1 minute
It has been known for several years, discussed regularly in all the relevant high-speed design books and found in practically all PCB design guidelines: A trace crossing a split or gap with reference planes is a major EMC design rule violation. Ignore this and you could significantly impact the return current and the noise behavior of the PCB.
Many of today’s electronics contain large ICs, such as FPGAs, ASICs, or off-the-shelf processors that use multiple voltage rails. To maintain control over manufacturing costs, few electronic designers can afford to use the space for a full reference layer to support all the required voltage rails, including the reference planes to support the needed return path. Often, designers have no alternative other than to place some signals that cross cutouts, gaps or voids underneath or above the routing path.
But what might be considered a small design rule violation can impact the signal integrity behavior of single-ended and differential signals, as well as the overall EMC fingerprints of the PCBs. Violations like this increase the chance that the entire system will fail EMC testing.Read the full article here.Editor's Note: This article originally appeared in the the April 2013 issue of The PCB Design Magazine.