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This column originally appeared in the November issue of The PCB Design Magazine.
Moats, islands, cut-outs in the ground plane, isolated power planes, floating ground regions, and a host of other intricate layout techniques are often used by PCB designers to reduce crosstalk, EMI, and to otherwise improve overall system performance.
But a high-speed signal crossing a split in the plane causes problems along at least three dimensions, including signal quality, crosstalk, and EMI. The problem is the impedance discontinuity in the signal path crossing the split. The discontinuity reflects energy back toward the source – particularly the higher-frequency components of the signal. At high frequencies, the return current follows the path of least inductance – which is directly below the signal trace – but that path is broken by the split. The reason for this discontinuity is the fact that the return current has to find an alternate path back to the source, creating a large loop area and a nice little antenna for differential-mode radiation.
It is important to keep in mind that both ground and power planes (any plane) can be used as the reference plane and return current path for a signal.
The key to a successful mixed digital/analog design is functional partitioning, understanding the current return path, and routing control and management – not carving up ground planes. It is always better to have just one single reference (ground) plane for a system.
I mentioned “plane jumpers” briefly in my recent column Mixed Digital Analog Technologies, where I said: “If a digital signal(s) must cross a split in the power reference plane a ‘plane jumper’ decoupling capacitor (100nF) can be placed close to the offending signal(s) to provide a path for the return current between the two supplies (e.g., 3.3V —||— 1.5V).”
Figure 1: The return current path uses the capacitor to bridge power reference planes.
In Figure 1, the gap totally isolates the power reference planes, so a plane jumper capacitor is used to allow the return current to bridge the gap in the planes from 3.3V to 1.5V. This is quite effective, but should be only used as a last resort, if you cannot avoid routing such a signal across the gap.
I must say that it does look weird – having a decap on the schematic between 3.3V and 1.5V, where decaps are normally placed between power and ground.
Figure 2: Control signals cross over the “bridge” of a split GND plane.
Figure 2 illustrates the correct way to tackle this situation – control signals crossing over the “bridge” of a split plane. The (blue) traces are grouped together, with a continuous ground plane beneath, providing a reliable return path for these signals. The trick is to always reference a signal to a solid plane – not to split the reference plane. The power plane can be split providing it is not used as a reference plane.
But that is the most basic use of a plane jumper. Let’s look at where else in the design these magic jumpers can be employed.
ICD recently simulated a board whose designers intended to route high-speed signals from a chip to a connector on top of the board. The routing fanned out from the BGA, went directly to layer 3, then popped back up through a via to a connector on the top layer. This seems perfectly reasonable.
But looking at the stackup in more detail, the signal was first referenced to the GND plane on layer 2; then, as it transitioned to layer 3, its reference plane changed to VCC (layer 4) due to proximity. There is, in this case, only one way for the return current to “jump” planes, and that is by finding the nearest VCC to GND decoupling capacitor – which may be a long distance (relatively) from the signal transient, creating a large loop area and undesirable common-mode currents. This can all be avoided by placing a plane jumper (decap), close to the signal-via transition, between VCC and GND.
In the case, where there are multiple ground planes on a PCB, we cannot simply assume that “ground is ground” and be sure that the return current will find its way back to the source. GND stitching vias should be placed next to each signal-via transition to stitch the GND planes together, providing a clear return path.
Figure 3: Signal current flow (red) and return current flow (blue).
Now, the designer had good intentions: using the GND plane on layer 2 as the common reference plane. Everything would be fine, until a lack of communication (and understanding of the design parameters) led the CAM engineer at the fabricator to change the thickness of the core and pre-preg materials to suit the dielectric materials they had in stock.
This is a classic case that we see all the time. It is the point where our design crosses over into the real world – manufacturing. It represents a point beyond which many designers rarely dare to venture, due to their lack of understanding of PCB fabrication processes. But, it is a fact that the more awareness we have surrounding the fabrication processes, the better our designs become, and the better designers we become.
The CAM professional looks at your board in purely physical terms. He, most likely, has no understanding of which signals are critical, and your current return paths. His window to your world consists of layers of dielectric materials, copper foils, PTH vias, and soldermasks. The standard Gerber file format – transferred from layout to fab – is a rather primitive (based on the old X,Y plotters) but highly effective format for describing two-dimensional graphical information. It is well suited for representing the two major components of a PCB image: lines and dots. But this is all they are to the CAM engineer.
The proverbial ”left shift” in the design process is to put control of the stackup build back into the hands of engineers and PCB designers – enabling them to collaborate with, if not control, the outcome of the fabrication. To do this, designers need a comprehensive list of standard dielectric materials from popular manufacturers like Isola, Nelco, Rogers, etc., and the ability to insert these into a prototype stackup, determining the single-ended and differential impedances of these materials combined with PCB layout design rules. The ICD Stackup Planner, shown in Figures 3 and 4 (available for download at www.icd.com.au) handles these tasks quite well, in fact, providing an interface between CAM, signal-integrity simulation, and PCB layout.
Since layer 3 is now closer to the GND plane on layer 2 in Figure 4, it will be used for the current return path, rather than VCC, as before. And, there is no need for plane jumpers in this case. This is by far the best scenario. The PCB designer can pass this information on to fabrication with confidence that his intended stackup build will be manufactured to suit the design’s electrical needs.
Figure 4: The return current path now uses a common GND plane (layer 2).
Plane jumpers can be used to easily resolve a return-current issue, but they are best avoided by taking control of the stackup back into the hands of the hardware engineer and PCB designer, while streamlining communication between the hardware-engineering team and fabrication.
Points to Remember
- A split in a plane causes an impedance discontinuity in the signal path crossing the split, creating signal reflections, crosstalk, and unwanted common-mode currents that can lead to EMI problems.
- Both ground and power planes (any plane) can be used as a reference plane and return current-return path for a signal.
- It is always better to have only one single reference (ground) plane for a system.
- Plane jumpers (ceramic decaps) can provide a path for the return current between the two supply planes.
- A bridge, provided by an adjacent plane, is best used for control signals to cross a split plane.
- Plane jumpers (decaps) can be placed close to a via to allow the flow of return current from plane to plane.
- Where there are multiple ground planes, ground-stitching vias should be placed next to each signal-via transition.
- The more knowledge PCB designers have of the fabrication processes, the better the outcome of our design, and the better designers we become.
- The “left shift” in the design process is to put control of the stackup back into the hands of hardware designer so that electrical design parameters don’t get pushed to the side.
“Advanced Design for SMT” two-day course – Barry OlneyBeyond Design: The Dumping Ground – Barry OlneyIntro to Board-Level Simulation and the PCB Design Process– Barry OlneyPCB Design Techniques for DDR, DDR2 & DDR3, Part 1 – Barry OlneyPCB Design Techniques for DDR, DDR2 & DDR3, Part 2 – Barry OlneyElectromagnetic Compatibility Engineering – Henry OttHigh-Speed Digital Design – Howard JohnsonThe ICD Stackup Planner and PDN Planner can be downloaded from www.icd.com.au
Barry Olney is managing director of In-Circuit Design Pty Ltd (ICD), Australia. The company developed the ICD Stackup Planner and ICD PDN Planner software, is a PCB Design Service Bureau, and specializes in signal integrity, crosstalk, and timing simulation, as well as EMC analysis.