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Chip and PCB Co-design: Cut Costs and Improve Quality
March 21, 2012 |Estimated reading time: 7 minutes
Nearly every integrated circuit made today ultimately finds its way onto a PCB. Despite this fact, most PCB designs are often an afterthought and never considered in the planning of the chip itself. The PCB is difficult to complete on a minimal number of layers and signal integrity is often compromised.
These problems can be solved by implementing a cross-domain co-design methodology that considers the physical layout requirements of the PCB (without looking over the package substrate) in the context of floor-planning the chip.
Figure 1: A well-coordinated co-design of chip, package, and PCB results in much easier routing and layout than what is traditionally required when there is little collaboration.
Next Generation Co-design
With the increasing I/O count on many SoCs and the growth in multi-die packaging (SiP), and 3D-IC (TSV), companies are recognizing the value of cross-team collaboration between the IC, package and PCB design groups. These designs drive engineers to reconsider how they plan and automate the I/O placement on their chips. In some instances, informal design flows based on multiple EDA design tools are starting to be pieced together. This is a step in the right direction; however, without a central repository for the data or accurate device models, design intent is often misinterpreted or lost and redundancy is often introduced into the flow.
There are several key ingredients to building a robust co-design solution. For starters, the design environment should be able to read/write data from all three design domains (IC, package and PCB). Leveraging industry standard formats (Verilog, VHDL, GDSII, Excel, AIF, etc.) is considered for automating this task.
Another integral piece of a cross-domain methodology is connectivity management. This is required to capture and manage the system level connectivity; that is, the connectivity that spans across the IC, package substrate and PCB. Since a signal name often changes between domains, automated pin mapping is required. Since recent trends for capturing connectivity for large ICs have focused on tables, large interconnect tables should be supported, as well as traditional graphic-based schematics. This should be a single design tool that supports a combination of both methodologies to support mixed-signal designs.
Often overlooked by the chip (and package design) team is the generation of the schematic symbol that is critical to the PCB design process. These symbols will often have hundreds or even thousands of pins. The signal assignments to these pins have the potential to change frequently in the co-design process. Not using an automated solution for this process would introduce the potential for human error into the co-design flow. Therefore, a complete co-design methodology must automate these updates. This process would provide the user the ability to divide the device into multiple symbols as required for fitting on the appropriate schematic sheet while adhering to company graphic standards.
Along with the connectivity that traverses these design domains are the design constraints. These would include local (specific to a single domain) as well as system level (cross-domain) rules. Defining and managing these constraints would need to be tightly linked with a connectivity management tool.
Generation of the physical devices in a co-design flow is equally important. Before any physical I/O and interconnect can be optimized, models must be available for the IC, package and PCB footprints. The IC footprint data would be included in the VDM and automation of this footprint is straight forward.
However, physical footprint data is also required for the package and the various PCB-level devices that will be used for optimization. In addition to the physical pin locations, it is important to include the break-out and fan-out routing for these devices. This data is critical for higher pin-count devices and should not be overlooked. Connectivity from the IC pad all the way through to the final PCB route destination is the ideal data set for I/O optimization.
Fortunately, most physical library data can be automatically generated by simple software algorithms based on user entered parametric data, or by reading existing spreadsheet part data. In addition, the ability to use the PCB design library for accurate board-level physical devices is important. In some cases, during early planning, abstract data could be used to represent the physical device when not readily available from a given design team. This capability is particularly useful for prototyping and feasibility studies. The ability to generate this data quickly and easily is important to a successful co-design methodology.
Once the data is captured, all three design teams would be able to view, in a single graphical environment, the complete interconnect path from on-chip I/O to flip-chip bump, to package pin and finally to PCB level pin displayed as a flight line. This ability to visualize the complete interconnect path across the system is the basis for robust interconnect planning. It also gives an early indication of the routing challenges on the PCB and package substrate leading to more accurate schedule and cost planning for the complete system.
The basis for I/O and interconnect optimization begins here. This is the process of unraveling the rat’s nest of flight lines across all three design domains. The random unraveling of interconnect across the system is not realistic. Multiple pin/signal/bus rules need to be applied at the IC, package and PCB levels. An advanced rule development capability that provides a straightforward way to constrain signals would support this. One example of this would be to set a pin adjacency rule for the positive and negative signals in a differential pair. Without a rule-based methodology for the unraveling process, the design teams would be required to lock down most of the signals in their design. This would greatly reduce the effectiveness of any co-design methodology.
Figure 2. A rule-based methodology for the unraveling process prevents designers from locking down most pins early in the design.
With the rules established, the optimization process could begin. The unraveling process could be run on entire signal paths across IC, package and PCB. For detailed optimization, the user would focus on a section of the interconnect path at a time. The unraveling algorithm supports a reduction in length or a reduction in flight line crossovers (layer reduction). This unraveling algorithm is the core of the methodology and once all of the data is available, it would likely be the most frequently used feature in the flow, providing layout specialists from each design domain the ability to quickly look at trade-offs between the IC, package and PCB layouts.
Starting with the PCB level devices and optimizing inward to the package and then to the IC produces the most efficient workflow. This approach has been shown to greatly reduce the cost and design cycles for the complete system. And with an accurate VDM in place, no significant impact on the IC would occur. The example shown uses a third-party DDR2 SDRAM device and PCI-Express connector to drive the optimization process from the board back up through the package onto the IC. The end result is a more routable PCB and package substrate with fewer layers (lower cost).
During these early planning stages, it is also the best time to start looking at system-level timing and potential signal integrity (SI) issues. Pre-route analysis could be performed by representing interconnect as estimated transmission lines, and simple lumped equivalent circuits. The results from any analysis run at this stage could be used to define constraints that would be used to drive the routing on the package substrate and PCB during final implementation.
This is also the ideal time to start to plan and analyze the power delivery network (PDN) across the PCB, package and onto the IC. Integration with an accurate power integrity (PI) tool could prove invaluable. Early analysis data could be used to drive the correct signal-to-power ratio for the flip-chip bump array mentioned above. It could also be used to make trade-offs between on-package and PCB level decoupling.
The Bottom Line
The overall cost of getting a chip shipped in volume is a concern for many companies in today’s market. The industry’s leading companies are starting to implement co-design flows in hopes of reducing overall design cycles and cost. In this column, I’ve proposed an approach to developing a co-design flow that is based on a new intelligent die abstract model (VDM) and a board-driven methodology. This methodology has been used to save over 25% on a high-volume production PCBs.
John Park is business development manager and methodology architect for Mentor's System Design Division.