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Note that I use the term “design for profitability,” or DFP, as opposed to any of the other acronyms such as DFM (design for manufacturability), DFT (design for test), or DFA (design for assembly). I’m taking this approach because it really all comes down to profit, doesn’t it?
Designers have the power to design profit into the board, or, conversely, inadvertently increase costs and remove profit from the PCB. In this article I am going to go over just a few of the challenges that fabricators routinely face and some typical solutions, especially solutions that can affect your bottom line.
I will start with DFM. Generally, this is the first stage for prototyping and DFM depends greatly on the capabilities of your chosen fab shop. Some designs are finished with autorouters after the critical traces have been hand-placed. It is at this point that unintended issues can arise between design and fab.
An example of this is same net-spacing violations where a track may “double back” near a surface mounted component, creating same-net spacing violations (Figure 1). Whereas the software does not see these as legit violations because they are same net, a fabricator knows that any features creating spaces below 0.003” can easily flake off at the image stage and create havoc elsewhere in the form of shorts. Edit time must be taken at the fab stage when these same-net spacing violations occur and the slivers eliminated. Some CAM software packages have a sliver fill option, but again this requires additional edit time at CAM.
Read the full article here.
Editor's Note: This article originally appeared in the March 2013 issue of The PCB Design Magazine.
Andy Shaughnessy, Design007 Magazine
We’re in the middle of show season, and it certainly “shows.” Thank you very much. I’m here all week. Don’t forget to tip your wait staff. This week, we published a variety of articles, columns, and news items, and much of it centered on trade shows. Technical Editor Dan Feinberg brings us a report from CES 2023. IPC announced the winners of the Best Technical Paper awards for IPC APEX EXPO 2023. And we have an interview with Altium’s Rea Callender about the company’s educational efforts at APEX and around the globe.
I-Connect007 Editorial Team
Altium keeps its eyes on the designers of the future. The company has been working with colleges and universities for years, providing free seats of Altium Designer for the next generation of PCB designers and design engineers. At IPC APEX EXPO 2023, Altium will be providing software for the finalists in the IPC Design Competition just as it did last year. They offer a variety of other educational programs as well, including Upverter classes and a design competition that aims to address environmental change. Here, Rea Callender, Altium’s VP of education, discusses its educational programs and plans for the week of the show.
Patrick Crawford, IPC
Last year, IPC held its first-ever design competition at IPC APEX EXPO in San Diego. PCB designers from around the world competed in a series of heats during the months before the show, culminating in a showdown on the show floor between the top three finalists. Rafal Przeslawski, now with AMD, took home the top prize last year. This year, the competition is back for its sophomore year. I asked Patrick Crawford, manager of design standards and related programs for IPC, to “layout” the details on the design contest, including lessons learned in 2022 and what’s new for the 2023 competition.