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SSO Noise, Eye Margin and Jitter Characterization
May 13, 2009 |Estimated reading time: Less than a minute
This paper, which won a Best Paper award at DesignCon 2009, describes the power integrity design and characterization for a single-ended I/O interface through noise, eye margin and jitter measurements. The frequency domain techniques are used for designing the I/O PDN. For PDN characterization, onchip PDN elements are extracted through the VNA measurements. The peak-to-peak voltage noise is measured on-chip at the driver. The eye margin reduction and jitter induced due to power noise are characterized versus frequency. The overall signature of the time domain noise, eye margin reduction and jitter response is well correlated with simulated impedance response.
Click here to read.