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Designers Council Seeks High-Speed Certification Input
October 23, 2008 |Estimated reading time: 5 minutes
As many of you know, the Designers Council has updated the Basic and Advanced Designer Certification training materials, and it is now time to move to the next phase of professional development. Your Education Committee has authorized development of the High-Speed - High-Frequency Focus Module for Certification.
Professor Rainer Thueringer, University of Giessen, Germany has already prepared several chapters of the information to be studied. He also helped to define the 32 topics to be covered in the two days of training review that make up a Certification Workshop. Now we need your input in order to move forward, so that the whole training module has a cohesive structure.
Here is your chance to participate. We are planning nine working weekends to prepare the syllabus, followed by five weekends to develop the questions and answers to be used in the exam. Each meeting will build on the previous effort. We will then schedule beta test sessions to fine-tune the relationship between study material and exam.
This is a great opportunity for professional development: build your credentials, collaborate with other industry experts, and make a real contribution to the design community. Volunteers will receive credit in the published materials, as co-authors of a particular section and/or as general contributors.
Designers who volunteer should have ideas about content for at least one of the 32 areas covered in the following Course Outline. Background in signal integrity and high-speed issues is most helpful. Volunteers may attend the working sessions in person or via teleconference. You may also send in your existing articles and/or presentations, with authorization for use in the Focus Module. Feel free to bring in colleagues with expertise in any of the areas covered by the Course Outline.
The following dates and locations have been suggested. They are coupled to scheduled IPC events in each area, but we are open to suggestions for alternate sites.
Please review the list below, and let us know by November 15, 2008 how you can participate.
Study Guide Preparation: 2009 Working Sessions
January 17-18, Orlando, FL
January 31-Feb 1, Austin, TX
February 14-15, Phoenix, AZ
February 21-22, Irvine, CA
March 14-15, Bannockburn, IL
April 18-19, Boston, MA
May 16-17, San Jose, CA
June 6-7, Toronto, Canada
June 20-21, San Diego, CA
2009 Test Question Preparation: Study Guide Review and Modification
July 25-26, Raleigh, NC
August 7-9, Seattle, WA
August 22-23, Bannockburn, IL
September 12-13, Philadelphia, PA
October 10-11, San Francisco, CA
October 24-25, Irvine, CA
2009 Beta Testing
November 9-11 [Beta #1], Seattle, WA
November 12-14 [Beta #2], Phoenix, AZ
November 19-21 [Beta #3], Fredericksburg, VA
December 3-5 [Beta #4], San Diego, CA
2009 Beta Test Results Analysis and Modifications
December 7-9, Beta Analysis, Bannockburn, IL
Course Outline
Certification Focus Module for High Speed - High Frequency
DAY 1
BASICS OF HIGH SPEED
- 1.1 High Speed Defined
- Low and High Frequency Signals
- Signal Rise Distance; Edge Rate
- Critical Line Length - Risetime Relationship
- Skin Effect; Signal Attenuation
- 1.2 Wave shape and Frequency
- Sine Wave Description
- Digital Pulses and Harmonics
- Time Domain and Fourier Spectrum; Bandwidth
- Clock Frequency vs. Switching Frequencies
- 1.3 Impedance Definition
- Line Impedance -Water model
- DC- versus Impulse Current
- Electrical Line Impedance; Lumped C,L
- Power Supply Impedance; Requirements
- 1.4 Transmission Line Definition
- Signals on TEM-Lines; Differential Signals
- Propagation Delay, Attenuation, Slewrate and Skew
- Reflections and Oscillations; Termination topic
- Coupled Lines; Crosstalk
ELECTRICAL REQUIREMENTS
- 2.1 Power System Implementation
- Distribution Path; Ground Bounce
- Bypassing/Decoupling
- 2-sided Boards
- Multilayer; Embedded Capacitor
- 2.2 Signal Transmission
- RF Signal Return Current
- Reflections and Oscillation
- Topologies and Terminations
- Crosstalk (Forward & Backward) & Control
- 2.3 Circuit Analysis
- Timing Margin; Clock Skew
- Loaded Line Characteristics & Timing
- Branching Issues; Stubs
- Layer Skipping
- 2.4 Differential Signaling
- Routing Techniques
- Terminations
- Influence of Planes
- Conductor Width & Spacing
BOARD CHARACTERISTICS
- 3.1 General PC Board Fabrication
- Standard Materials (Laminates & Prepregs)
- Material Properties (DK, CTE, ...)
- Copper Requirements; VLP Foils
- Process Tolerances & Influence Analysis
- 3.2 Board Impedance
- Impedance Classes
- Single Ended Layering (Microstrip and Stripline)
- Differential Pairs
- Power planes
- 3.3 Multilayer Constructions
- 4 Layer Structures
- 6 Layer Construction
- 8+ Layer Constructions
- Layering Approaches
- 3.4 HDI-Microvia Constructions
- Microstrip Constructions
- Stripline Constructions
- Dual-Stripline Constructions
- Impedance Variations & Tolerances
LAYOUT PRINCIPLES
- 4.1 PC Board Design Elements
- Optimum Impedance Value
- Proper Trace Width & Spaces
- Maximum Stub Lengths
- Test Structures needed
- 4.2 Component Placement & Splitting Planes
- Circuitry Analysis; Busstructures
- Split GND/VCC PLanes (® Martin O'Hara et.al.)
- Component Side Distribution
- Peripherie & Connectors
- 4.3 Vias & Via Chains
- Mechanical Properties
- Capacitance & Inductance of Vias
- Influence on the Line Impedance
- Return-Current Flow
- 4.4 Prelayout Analysis (Line Simulation) (® Freddie)
- Layer Stacking Strategy
- Timing, Clock Distribution
- Termination Strategies; Noise Budgets
- Preventive Crosstalk Analysis
DAY 2
COMPONENTS AND ASSEMBLY
- 5.1 Bypassing/Decoupling Capacitors (® Rainer + O'Hara)
- Real Capacitors; Impedance vs. Frequency
- Dielectric, ESR & Loss Tangent
- Parallel Connection of Capacitors
- Optimal on Board Contacting
- 5.2 Component/Package Selection
- Parasitic Package Inductance & Capacitance
- Electrical Values: Rise time, Slew rate, Noise Margin, Driving Force
- Fanout Wiring Requirements & Stub Length
- Embedded Passives, COB
- 5.3 Connector Systems (® Howard Johnson)
- Mutual Inductive Coupling & Parasitic Capacitance
- High Speed Connectors
- Estimating Crosstalk
- Return-Current Path
- 5.4 Ribbon Cables (® Howard Johnson)
- Signal Propagation
- Frequency Response
- Cable Rise time
- Cable Crosstalk
PERFORMANCE PARAMETERS
- 6.1 Concurrent Layout Analysis (Line & Board Simulation) (® Freddie)
- Component IBIS Models; Loads, Terminations
- Timing/Delay/Skew Optimization
- Crosstalk & Reflections Analysis
- Power Distribution System: Integrity Analysis; Decaps
- 6.2 Optimum Layer Relationship
- Signal Layer Distribution; Shielding Planes
- Spliting Planes; Cutouts, Field Fringing (® Martin O'Hara et.al.)
- Crosstalk in GND Planes (® Howard Johnson)
- Stack-up Balance, Producability
- 6.3 Material Properties & Selection
- High Speed Dielectric Material
- RC-Foil vs. Reinforced Material
- Copper Thickness vs. Line-width
- Thermal Management; Heatsinks
- 6.4 Costs, Availability, Lead-time
- Influence Layer Count & Line-width
- HDI/µVia vs. Conventional Boards
- Intermixing High Frequency Materials
- Back Drilling for Stub Removal
ANALYSIS AND VERIFICATION
- 7.1 Post Layout Analysis (Board Simulation)(® Freddie)
- Power Integrity: Decoupling & Noise Margin
- Signal Integrity: Crosstalk & Reflections
- Constraint Driven Routing Analysis
- Delay/Skew Situation
- 7.2 Signal Integrity Measurements
- Defining Test Equipment
- Performance Parameters
- On-Board Measurements
- Interpretation & Consequences
- 7.3 Impedance Control Testing
- Test Setup Methods
- Coupon Design and Placement
- Testing Differential Pairs
- On-Board Measurements
- 7.4 Assembly Analysis Verification
- Registration Capability
- Testpoints and Test Nets
- Embedded Passives
- External Shields & Coating
DOCUMENTATION
- 8.1 General Documentation Practices
- Mixture of Electronic and Hard Copy Data
- Re-procurement of "as- built" requirements
- Configuration Management Strategy
- Field Reports and Maintenance
- 8.2 Materials/Impedance Tolerance
- Dielectric Parameter Descriptions
- Maximum Allowance for Performance Variation
- Coupon Verification Strategy
- Prototype and High Volume Description Controls
- 8.3 Multilayer Construction
- Single Lamination Criteria
- Sequential, build-up Multilayer
- Embedded Passive Description and Control
- Exotic Material Influence/Definition
- 8.4 Board & Assembly Thickness Issues
- Limitation for Card Edge Conditions
- Assembly Support and Housing Influence
- Moisture Influence & Conformal Coating Descriptions
- Sequencing of Material, Fabrication, Assembly and Test
DAY 3
CERTIFICATION TESTING
To volunteer, contact IPC Professional Development at AnneMarieMulvihill@ipc.org or +1 847 597 2827 .
We look forward to hearing from you, and will keep you informed about progress in the development of this new Designer Council Certification activity.
Dieter Bergman
IPC Director of Technology Transfer