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PCI Express Timing Margins
October 15, 2008 |Estimated reading time: Less than a minute
This case study takes two PCI Express high-speed serial interfaces through a detailed exercise of quantifying individual contributors to operating margin erosion using the metrics of jitter, S-parameters and time-domain reflectometry. This paper, written by Senior Engineer Greg Edlund of IBM Global Engineering Solutions, was presented at DesignCon 2008. Click here to read.