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A New Process for Fabricating Low Cost Advanced Interconnects
August 24, 2007 |Estimated reading time: 6 minutes
Almost regardless of the industry or application, the unrelenting drive towards higher speeds and frequencies, greater I/O densities and functionality, while at the same time lowering costs, has driven the PCB industry in many new directions. Certainly the universal focus on lower prices has forced fabricators to embrace lower labor cost models in new locations across the globe. The technology advances required for today's complex interconnect structures has brought with it the need for HDI processes, microvias, new process/material types and thinner materials. The interconnect industry is always hungry for new ways to cut labor out of the cost of a part and improve quality, although what is really needed is a new paradigm, a new way to create value by producing advanced interconnects that doesn't necessarily rely only on traditional PCB processes to create vias and traces.
The drive to embrace new PCB technologies can be found in many markets and applications. Although not traditionally thought of as early adopters, modern Defense/Aerospace programs for high frequency antennas, device packages and other advanced interconnects are embracing newer material systems and fabrication techniques to reduce weight and improve performance of their systems. Leading edge medical ultrasonic imaging, automotive collision avoidance and commercial device packaging designs has similar challenges, which is pushing designers and fabricators to the some of the newer solutions that are being offered by our industry. The desire for cost effective RFID tags has many companies exploring different ways to produce them. Much has been written recently about applying new ink jet printing technology to PCB fabrication, or the Occam Process, which reverses the generally accepted method for building interconnects. These are both good examples of our industries healthy drive towards improvement and a more certain future, whether it's evolutionary or revolutionary.
A relatively recent addition to the high performance circuit materials marketplace is liquid crystal polymer (LCP) laminates. Manufactured now by multiple sources, they offer very thin dielectrics, high performance electrical properties, very low moisture absorption and gas transmission. This new material system is finding a home in many applications, ranging from hearing aids to radar antennas. Dynaco has successfully pioneered the circuit technology useful for fabricating multilayer interconnects with LCP in recent years and has developed a number of licensable patent pending processes as a result.
Dynaco has also recently developed a revolutionary new process that potentially goes much further than ink jet technologies to cost reduce traditional PCB processes for flex, rigid or rigid-flex constructions. Newer ink jet technology, while certain to provide some cost benefits to fabricators, do suffer from some uncertainty related to electrical performance, reliability and cost. It remains to be seen if the promise of cost effective ink jet based circuit fabrication can be realized in volume roll to roll technology. The new Dynaco process, called DEP (Direct Emulsion Plate), has demonstrated an ability to create multilayer circuit interconnects without laminating, etching copper or drilling vias. Beyond eliminating these costly processes and their associated support process costs, the DEP process also aids in improving feature registration on thin dielectrics, such as LCP or Dupont Kapton. Use of the process would also reduce the cost of the materials used to fabricate circuit boards, since unclad materials are used in place of copper clad laminates. The DEP process is capable of implementation and simplification of high volume roll-to-roll operations or in conventional panel based manufacturing.
In its most basic form, an unclad substrate is coated with a photosensitive material, imaged directly, developed and plated. Gone are dry film photoresist, dry film photoresist lamination / developing /stripping, copper foil, copper foil etching and spent etchant waste treat (See Figure 1). The DEP process is capable of providing very thin copper layers of 1-10 microns in thickness on very smooth dielectric surfaces, which can reduce electrical losses due to copper surface roughness. This thin electroless copper plating also lends itself to the realization of fine circuit traces down to 25 microns, depending on the imaging process used. The feature sizes and metallization thicknesses achieved are of a scale that can bring PCBs into the range of thin film circuit technology. Alternatives to copper plating have also been demonstrated, including directly plated gold or nickel-gold on DEP. The DEP process chemistry contains no polymer additives, is not solvent based and is readily available in volume today. Initial calculations of material costs to image and metallize any given layer with the DEP process are approximately 30% of conventional layer process costs for a copper metallization of 1-2 microns.
Figure 1: Layer Process ComparisonDEP multilayer circuits are formed by using a flexible, photoimageable covercoat material to form the next dielectric layer and any openings for "vias" or layer to layer solid plated interconnects (See Figure 2). Subsequent DEP additive plating steps and additional coating steps of photoimageable covercoat complete a multilayer stack.
Figure 2: Multilayer DEP Process FlowWith this method, conventional lamination processes are no longer required (See Figure 3). We can envision a self contained manufacturing cell that can manufacture DEP process multilayer circuits by cycling through the appropriate coating, imagining and plating operations. The Multilayer DEP process can be used as an alternative to LTCC, finally providing the long sought after LTCC advantage of stacked vias to the PCB fabricator. Achieving HDI structures with DEP processes is achievable without utilizing laser vias for very high density interconnect structures.
Figure 3: Multilayer DEP Process vs. Conventional PCB Process ComparisonTesting performed to date has shown the Dynaco DEP process to yield perfectly acceptable copper peel strengths on a variety of advanced dielectric substrates, as shown in Figure 4. Circuits fabricated with DEP processes have exceeded many of the military specification requirements found in conventional MIL-PRF-55110 and MIL-P-50884 manufacturing, including passing solder float testing and repeated exposures to solder temperatures as well.
Figure 4: Peel StrengthsCurrent development testing includes verifying DEP copper loss performance at high frequency on unclad low loss substrates and the use of direct metallization of gold for medical sensors and ultrasonic imaging applications. Additionally, we are investigating the use of other photoimageable dielectric materials for the multilayer DEP process to achieve the DEP Multilayer Concept as shown in Figure 5.
Dynaco has developed and replicated the DEP process and is currently optimizing the process for several real world applications. The DEP process, whether used to fabricate single layer circuits in high volume or to enable thin, high density advanced multilayer interconnects, has the potential to significantly alter common printed circuit board manufacturing cost structures. The DEP process has the potential for implementation in other process technologies, which could include thin film, LTCC and HTCC. The developers of DEP are in early discussions with several potential partners to help accelerate the entry of the process into production operations at multiple facilities.
Figure 5: DEP Multilayer Concept For additional information or a copy of this article, please visit www.DynacoCorp.com or send an email to GoDEP@DynacoCorp.com.
About Dynaco: Dynaco Corp. is a premier specialty fabricator of flex, rigid-flex and rigid circuits and custom assemblies that focuses on the military/aerospace marketplace. The company processes a wide variety of material types and has recently become the worldwide leader in the fabrication of Liquid Crystal Polymer (LCP) multilayer circuits. Located in Tempe, Arizona, Dynaco is an ISO 9001:2000 facility and is an SBA certified Small Disadvantaged Business (SDB).