Cadence Introduces EMX Designer


Reading time ( words)

Cadence Design Systems, Inc. announced the new Cadence® EMX® Designer, a passive device synthesis and optimization technology that delivers, in split seconds, design rule check (DRC)-clean parametric cells (PCells) and accurate electromagnetic (EM) models of passive devices, such as inductors, transformers, T-coils and more. Seamlessly integrated with the Cadence Virtuoso® ADE Product Suite, the EMX Designer solution offers more than 10X faster synthesis times, with significant productivity gains versus other solutions.

The EMX Designer solution lets customers rapidly synthesize DRC-clean passive devices at a touch of a button, based on electrical and geometrical requirements. With unparalleled flexibility, EMX Designer PCells can easily be modified to meet the designers’ exact layout requirements, utilizing a long list of options from a user-friendly interface inside the Virtuoso platform. When used with the EMX 3D Planar Solver, the industry’s gold-standard electromagnetic modeling engine, the EMX Designer solution ensures the accuracy of generated models. The seamless integration with the Virtuoso platform offers users various options for plotting and appending results.

“pSemi evaluated the Cadence EMX Designer solution as we were interested in automating the passive device creation and optimization process for our proprietary PDKs,” said John Sung, Vice President of Engineering Infrastructure at pSemi. “EMX Designer fully met our requirements for PCell flexibility, speed and accuracy. It is seamlessly integrated into the Cadence design flow and will improve the productivity of our design teams.”

“The new EMX Designer solution adds key technology to our leading Custom IC design flow, delivering the most flexible passive-device PCells in record-breaking time while also enabling significant productivity gains,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “We are pleased to offer our customers an expanded, complete, highly differentiated and efficient IC design platform that addresses the early stages of the design all the way through to signoff and closure.”

“Using Cadence’s new EMX Designer solution, our team was able to improve productivity and reduce design cycle times,” said Peter Gammel, CEO, Ubilite. “We managed to synthesize passive devices with better performance, and at the same time, save 20% silicon area for the advanced process nodes we use with the new solution. EMX Designer offers us a versatile library of passive devices, delivering extremely accurate results across all process nodes at incredibly fast speeds.” 

The EMX Designer solution seamlessly interfaces with Cadence EMX 3D Planar Solver and further supports the Cadence Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence and system innovation.

Share




Suggested Items

DFM 101: Final Finishes—OSP

03/09/2023 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. The next final finishes to discuss in this series is OSP. As with all surface finishes there are pros and cons with the decision of which to use. It is a combination of application, cost, and the properties of the finish. OSP is RoHS-compliant as there is zero lead content in the finish.

A Sneak Peak with Jim van den Hogen

12/29/2022 | Andy Shaughnessy, Design007 Magazine
Jim van den Hogen has been teaching PCB designers and design engineers about fabrication processes for decades. Twenty years ago, I had the opportunity to see a class of his at PCB West; even back then, the room was jammed with designers eager to learn more about DFM techniques. Now Jim is bringing his teaching expertise to IPC APEX EXPO 2023 this January with a similar class directed at PCB designers. I asked Jim to give us a sneak peek into his curriculum and to share what he hopes attendees will take away from his class, as well as his thoughts on how to best bridge the gap between design and fabrication.

Workflow Challenges in Fabrication

12/22/2022 | Andy Shaughnessy, Design007 Magazine
Paul Cooke, the senior director of business development for Ventec International Group, is presenting a class at IPC APEX EXPO 2023 that looks at workflow challenges in fabrication, and the myriad drivers that can affect yield, reliability, and cost. Here he discusses the details of this Professional Development course, what he hopes attendees will take away, and why designers and design engineers would benefit from this class.



Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.