Shrinking Geometries: Back to Fundamentals to Fight EMI


Reading time ( words)

When silicon shrinks, a variety of things can happen—some positive, some negative. But for PCB designers, the fight against EMI becomes more complex as signal channels shrink and rise times increase. 

Dan Beeker is technical director at NXP Semiconductors, a veteran design engineer, and an instructor who has spent years helping students and customers battle EMI through building a better understanding of electromagnetic fields and field theory. In this interview, Dan explains what happens when silicon shrinks, how feature size controls signal speed, and why this marks the perfect time to return to the fundamentals of physics and field theory.

Andy Shaughnessy: Shrinking silicon is increasingly causing EMI issues for PCB designers and EEs. What sort of problems does shrinking silicon cause?

Dan Beeker: Smaller device geometries and higher current switching capabilities have thrust us all into the world of RF, HF, UHF, and microwave energy management. Rise times on even the lowest-tech devices now exhibit gigahertz impact. These changes directly impact product functionality and reliability. When IC technology was described as a percent of shrink from integer design rules, a circuit-based approach was usually close enough. Now that IC technology is described in nanometers, that traditional approach completely falls apart. An EM field, physics-based approach is essential. 

To make things worse, EMC standards have changed; we now have lower and higher frequency compliance requirements, much lower emissions levels allowed, and greater immunity required. The playing field and the equipment have completely changed. This really is a brand-new game. The challenges are not only about providing adequate power to the devices, but also managing the output signals. The smaller the transistor, the faster it turns on, and the bigger the impact it has on EMC and signal integrity. 

To read this entire interview, which appeared in the February 2023 issue of Design007 Magazine, click here.

Share




Suggested Items

Simplifying Simulation and Analysis

04/25/2023 | Andy Shaughnessy, I-Connect007
Simulation has always been a critical step in the design process, and it’s only become more critical as design methodologies have become more complex. Gone are the days when simulation meant a simple logic simulation of your circuit, or a basic SPICE run to check signal waveforms. The simulation complexities that are required often fall “above the paygrade” of all but the most experienced members of a hardware design team. So how do you keep simulation from becoming a design bottleneck?

Better Engineering Through Artificial Intelligence

04/10/2023 | Andy Shaughnessy, Design007 Magazine
At DesignCon 2023, I spoke with Cadence Design Systems’ Brad Griffin about artificial intelligence and machine learning as engineering aids for signal and power integrity optimization. Brad makes the case that artificial intelligence methods, when added to optimizing tools in the design flow, can help engineers to evaluate a larger number of potential solutions, and zero in on more highly optimized solutions than they may have found on their own.

Advanced Packaging Means Advanced Routing Issues

01/26/2023 | Kris Moyer, IPC
In today’s ever-shrinking world of electronics designs, the use of BGA parts with very fine pitch features is becoming more prevalent. As these fine-pitch BGAs continue to increase in complexity and user I/O (number of balls), the difficulty of finding escape routes and fan-out patterns increases. Additionally, with the shrinking of silicon geometry leading to both smaller channel length and increased signal integrity issues, some of the traditional BGA escape routing techniques will require a revisit and/or adjustment to allow for not only successful fan-out, but also successful functioning of the circuitry of the BGA design.



Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.