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When silicon shrinks, a variety of things can happen—some positive, some negative. But for PCB designers, the fight against EMI becomes more complex as signal channels shrink and rise times increase.
Dan Beeker is technical director at NXP Semiconductors, a veteran design engineer, and an instructor who has spent years helping students and customers battle EMI through building a better understanding of electromagnetic fields and field theory. In this interview, Dan explains what happens when silicon shrinks, how feature size controls signal speed, and why this marks the perfect time to return to the fundamentals of physics and field theory.
Andy Shaughnessy: Shrinking silicon is increasingly causing EMI issues for PCB designers and EEs. What sort of problems does shrinking silicon cause?
Dan Beeker: Smaller device geometries and higher current switching capabilities have thrust us all into the world of RF, HF, UHF, and microwave energy management. Rise times on even the lowest-tech devices now exhibit gigahertz impact. These changes directly impact product functionality and reliability. When IC technology was described as a percent of shrink from integer design rules, a circuit-based approach was usually close enough. Now that IC technology is described in nanometers, that traditional approach completely falls apart. An EM field, physics-based approach is essential.
To make things worse, EMC standards have changed; we now have lower and higher frequency compliance requirements, much lower emissions levels allowed, and greater immunity required. The playing field and the equipment have completely changed. This really is a brand-new game. The challenges are not only about providing adequate power to the devices, but also managing the output signals. The smaller the transistor, the faster it turns on, and the bigger the impact it has on EMC and signal integrity.
To read this entire interview, which appeared in the February 2023 issue of Design007 Magazine, click here.