The Test Connection: Spreading the Word About DFT
December 7, 2022 | Andy Shaughnessy, PCB Design007Estimated reading time: 3 minutes
As signal speeds continue to increase and feature sizes decrease, PCB designers are beginning to pay greater attention to test and design for test (DFT) strategies. Bert Horner, president of The Test Connection in Hunt Valley, Maryland, is spearheading this drive to show designers the benefits of a solid DFT plan, as well as the downside of not having a test strategy.
I met with Bert at PCB Carolina, where he was exhibiting and presenting a paper during the conference. We discussed his presentation, as well as why designers need to understand test and DFT issues, and why we need to see the PCB as one small—but very important—part of the entire system.
Andy Shaughnessy: Bert, it’s nice to see you. It’s been a while.
Bert Horner: Thank you for speaking with us today. It’s been a really good show.
Shaughnessy: Yes, it’s packed in here. You just gave a presentation, so why don’t you tell me about your class content and the response you received?
Horner: The Test Connection sees an opportunity to promote test strategy and design for test. As you know, we’re working with I-Connect007, writing a book about testing. I took a subset of that on test strategies for my presentation here today. It whets their taste buds and incorporates a thought pattern on test—starting with the design process. We hope it’s a good starting point for what we will cover in the book on test strategies. Right now, we’re at a point where we can bring that to fruition with some designers. Designers don’t always know what is happening on the back end, so we want to help them get more familiar with test protocols and test solutions and inspection as well.
Shaughnessy: For a lot of designers, test has traditionally been something of an afterthought.
Horner: Yes. We’re trying to encourage the design for test (DFT) with a test strategy that starts as early as the schematic level. We use ASTER TestWay, but Siemens EDA has a similar tool and there is another tool out there as well. Designers are starting to address this. We think they can save money in the long term by spending a little bit of time and money throughout the design process.
Shaughnessy: I heard that one attendee asked a question, and it triggered a long Q&A session.
Horner: Yes, we had a question about in-circuit test and boundary scan being done at the same time, which started a snowball of questions, and it was a lot of exciting conversations. It wasn’t just me and the audience, but audience member to audience member. It’s fun to be involved in those kinds of presentations, and I could see that there was a demand for DFT and test strategies among designers.
Shaughnessy: It sounds like there’s a definite thirst for knowledge about test.
Horner: It’s time, and we’re here to quench that thirst. They’re seeing that DFT can save them time and effort, and the exposure of lost revenue and the fear of being known in the industry for shipping a bad product goes a long way.
Shaughnessy: Right. A lot of people just looked at it as test. It wasn’t seen as a value add because it’s not necessarily making the board “better,” but you’ve got to look at it from a big picture perspective.
Horner: Yes, that’s right. The board is only a component of the whole system, and if you don’t build that component, you run the risk of not having a working unit.
Shaughnessy: How has your year been going at Test Connection?
Horner: For Test Connection, 2022 has been a very good year for us. We continue to see growth. We do see the supply chain challenges, but we’re able to navigate through this and be able to offer a test solution in a timely fashion.
Shaughnessy: Great. Anything else you want to add?
Horner: The economy is always in question, but the industry as a whole is undergoing a bit of a renaissance, as we hope some of the technology comes back to North America. We’re positioned to help support that need.
Shaughnessy: All right. Good talking to you.
Horner: You too, Andy.
Suggested Items
Cadence Unveils Palladium Z3 and Protium X3 Systems
04/18/2024 | Cadence Design SystemsThe Palladium Z3 and Protium X3 systems offer increased capacity, and scale from job sizes of 16 million gates up to 48 billion gates, so the largest SoCs can be tested as a whole rather than just partial models, ensuring proper functionality and performance.
Signal Integrity Expert Donald Telian to Teach 'Signal Integrity, In Practice' Masterclass Globally
04/17/2024 | PRLOGDonald Telian and The EEcosystem announce the global tour of "Signal Integrity, In Practice," a groundbreaking LIVE masterclass designed to equip hardware engineers with essential skills for solving Signal Integrity (SI) challenges in today's fast-paced technological landscape.
On the Line With... Podcast Talks With Cadence Expert on Manufacturing
04/18/2024 | I-Connect007In “PCB 3.0: A New Design Methodology: Manufacturing” Patrick Davis returns to the podcast to talk about design rules. As design considerations become more and more complex, so, too, do the rulesets designers must abide by.
Designing Electronics for High Thermal Loads
04/16/2024 | Akber Roy, Rush PCB Inc.Developing proactive thermal management strategies is important in the early stages of the PCB design cycle to minimize costly redesign iterations. Here, I delve into key aspects of electronic design that hold particular relevance for managing heat in electronic systems. Each of these considerations plays a pivotal role in enhancing the reliability and performance of the overall system.
I-Connect007 Editor’s Choice: Five Must-Reads for the Week
04/12/2024 | Nolan Johnson, I-Connect007As we publish this week’s most-read news, the I-Connect007 team is wending its way home from an eventful and productive week at IPC APEX EXPO in Anaheim, California. We’ve posted a variety of dispatches from the show this week, released 73 realtimewith.com video interviews (and counting), and also gathered the content and updates you’ll be looking for in the upcoming issue of Show & Tell… IPC APEX EXPO 2024.