Does Copper Pour on a Signal Layer Decrease Signal-To-Signal Isolation?

Reading time ( words)

Does putting a ground pour on PCB signal layers make the isolation better or worse? It can go either way, but with the proper knowledge and application, this technique will improve your designs.

In this article, I’ll discuss how to simulate trace-to-trace isolation with true electromagnetic simulation software. We’ll also cover a variety of rules of thumb that can help you stay away from trouble.

Fact or Fiction?
Recently an acquaintance told me, “I have heard that putting a copper pour on a signal layer between traces actually makes the isolation between the traces worse.” I grabbed one of my RF boards and said, “If that is so, then how do all these RF boards that I have done with co-planar waveguide over ground manage to function? They all have copper pours on the signal layer, and they work to very high frequencies.”

Since co-planar waveguide over ground (CPWG), which is essentially “pouring copper on a signal layer,” is used for a lot of RF work, and is proven to work for very high-performance RF circuits, how did this contradictory opinion catch on in the industry?

To investigate this, I used a one-inch section of 50-ohm microstrip consisting of an aggressor trace from ports 1 to 2 and a victim trace running in parallel from ports 3 to 4. I used typical values for the dimensions as might be on a real PCB. The trace width is 20 mils, with a spacing of 60 mils from center to center, over an FR-4 substrate, 9.5 mils thick, with a modeled Er of 4.4.

To read this entire article, which appeared in the March 2022 issue of Design007 Magazine, click here.


Suggested Items

Webinar Review: Thermal Integrity of High-Performance PCB Design

08/01/2022 | Andy Shaughnessy, Design007 Magazine
Electrical and mechanical engineers may be working on the same product development teams, but they speak different languages, and they have completely different objectives. As a result, these folks almost never use the same software tools. But Cadence’s new Celsius Thermal Solver is an exception to the rule. In a new CadenceTECHTALK webinar, “How Static and Dynamic IR Drop Analysis Can Help PCB Designs and Challenges,” product manager Melika Roshandell and SerDes SI/PI engineer Karthik Mahesh Rao explain how the EE and ME can both use the Celsius Thermal Solver to achieve their disparate objectives.

Pulsonix Collision Avoidance to Bring Mechanical Capabilities Into ECAD

05/19/2022 | I-Connect007 Editorial Team
The I-Connect Editorial Team recently spoke with Bob Williams, managing director of Pulsonix. He discussed some of the new features in the upcoming version of the Pulsonix PCB design tool, Version 12, including collision avoidance and other 3D options that allow certain MCAD functions within the ECAD environment.

A Textbook Look: Signal Integrity and Impedance

05/18/2022 | Pete Starkey, I-Connect007
Believing that I knew a bit about signal integrity and controlled impedance, I was pleased to take the opportunity to connect with an educational webinar that I hoped would extend my knowledge. In the event I was surprised at how little I actually knew, and the webinar was an excellent learning opportunity. The webinar was introduced and expertly moderated by Anna Brockman of Phoenix Contact in Germany.

Copyright © 2022 I-Connect007. All rights reserved.