Living in a Material World: High-Speed Design Strategies


Reading time ( words)

Any discussion about high-speed PCB design techniques would be incomplete without considering the properties and requirements of the materials. Your material selection drives much of your design strategy when you’re operating at 28 gigabits per second or faster.

We recently spoke with high-speed design expert Lee Ritchey of Speeding Edge, and electronic materials veteran Tarun Amla of Avishtech and Thintronics, about the relationship between advanced PCB materials and high-speed design techniques. They discuss the challenges facing designers and engineers working with materials at speeds that were considered unreachable not long ago, and what designers need to know about material selection as board speeds continue rising toward the stratosphere.

Andy Shaughnessy: Would you set the stage by explaining the last few decades of materials that got us to where we are now and how designers are having to learn these EM properties?

Lee Ritchey: I joined 3COM in 1996 where we were doing reasonably well making all the lengths work at 10 megabits per second. And then I got started working on 100 megabits, and that was thought to be pretty fast. At that point, the only thing we were worried about was reflections and crosstalk, which basically meant impedance. In the laminates, we worried about whether we could get repeatability on impedance with a cross-section. And by 1998, I helped a startup build us a product where we had the links leaving the box at a gigabit per second. That was thought to be magical, and of course it was, in that context.

It wasn’t very long before I went to a startup called Procket Networks, where all the internal signals were 3.125 gigabits per second, and that was where we first started to worry about things like loss. Until then we hadn’t worried much about any of those properties. We worried about losses because the transceiver sets were not very good, so they couldn’t tolerate much. For example, a 10 dB loss was a big number, and so that’s when we started driving the laminate manufacturers to reduce loss. At the time, the only material that was considered low-loss was Nelco 4000-13 SI, and they achieved it by using a low-loss glass. That worked just fine until the tsunami happened in Japan, and Nittobo, the one supplier of that glass, was inside the quarantine zone. Within a week none of us could build our products anymore because we were all single-sourced with that glass.

I got involved with Isola to see if we could do something about it. It wasn’t too long before we were doing 10 gigs, and it surprised me that we soon were doing 100 gigs. The current links, the undersea cables all around the world, are 400 gigabits per second, which is pretty astonishing. We are achieving that with eight links of 56 gigabits per second, which pushed every single thing about the laminates. The industry wants us to double that, and to do that we’re using PAM4 (pulse-amplitude modulation), a four-level coating so that the clock is still 28 gigahertz. For us, the loss problem is still the same, but the noise margin, because the levels are smaller, is such that the error rate is not good enough right now. This is where I’m pushing material, now that we know the industry is going to want that.

Tarun_Amla_250.jpg

Between 1996 and 2021, we went from 10 megabits per second to 400 gigabits. That’s a 40,000X increase in bandwidth in 25 years. To do that we have pushed everything about the laminate. Tarun is probably the most renowned at doing that because he’s been the major player driving that whole thing. There are two things that I worry about. One is skew, which is glass weave that causes the two sides of the differential pair to not arrive at the same time, and then the link won’t work. The other is loss. Tarun, you can pick up the ball.

Tarun Amla: I remember around 2002 where people said that five gigabits per second was going to be unattainable in copper. There was a lot of work done around using optical channels which did not get much traction. Around that time, the RoHS lead-free legislation was coming on board, and that just added another layer of complexity, because not only did you want these signals to go through at those high data rates, but you also wanted reliable performance. Boards now had to go through 6X reflow at 260ᵒC for qualifications. In some cases, the qualification standards are about 10X reflow or even higher. Now I’m hearing about 20X reflow, which seems weird. Why would you want to do that to your board?

We are at a crossroads where we have to look at the next generation. Sadly, finding an alternative for copper is going to be difficult with the amount of work involved. A materials—dielectric—solution has to come through, or it will be like what happened with Moore’s Law. We are at an impasse because we have reached the limits, especially with 112 gigabits per second. If you’re trying to do it with PAM4, like Lee said, the margins are lower and you’ve got this inherent skew in that signaling, so that’s where it stands. The whole industry is waiting, and whether it’s 5G or 112 gigabits per second, the stage is set for something new to happen.

Happy Holden: The people I worked with in Taiwan making the flip chip substrates have been doing 8- to 15-micron lines as a basis for almost the last 15 years. Although they use a BT core and BT prepreg, they never got very good yields once they got under 20 microns, until they switched to using the Ajinomoto build-up film. Today, all eight of the Asian manufacturers of high-density packages use the ABF material primarily because it’s a very well-engineered resident system that’s robust, but it goes down extremely flat. That planarity is required for high density of imaging and developing, as well as etching. So, 20 microns is considered about the best you can do if you use laminate and prepreg. Below that and you have to start going to these engineered liquids or films that the Japanese perfected initially, and now other sources are available for them. That’s true for the thin film.

To read this entire conversation, which appeared in the January 2022 issue of Design007 Magazine, click here.

Share




Suggested Items

DFM 101: Final Finishes: OSP

03/09/2023 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. The next final finishes to discuss in this series is OSP. As with all surface finishes there are pros and cons with the decision of which to use. It is a combination of application, cost, and the properties of the finish. OSP is RoHS-compliant as there is zero lead content in the finish.

DFM 101: Final Finishes—HASL

02/14/2023 | Anaya Vardya, American Standard Circuits
One of the biggest challenges facing PCB designers is not understanding the cost drivers in the PCB manufacturing process. This article is the latest in a series that will discuss these cost drivers (from the PCB manufacturer's perspective) and the design decisions that will impact product reliability.

Advanced Packaging Means Advanced Routing Issues

01/26/2023 | Kris Moyer, IPC
In today’s ever-shrinking world of electronics designs, the use of BGA parts with very fine pitch features is becoming more prevalent. As these fine-pitch BGAs continue to increase in complexity and user I/O (number of balls), the difficulty of finding escape routes and fan-out patterns increases. Additionally, with the shrinking of silicon geometry leading to both smaller channel length and increased signal integrity issues, some of the traditional BGA escape routing techniques will require a revisit and/or adjustment to allow for not only successful fan-out, but also successful functioning of the circuitry of the BGA design.



Copyright © 2023 I-Connect007 | IPC Publishing Group Inc. All rights reserved.