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The newer industry-standard SerDes protocols such as PCIe Gen6, USB4, and the 100G per-lane Ethernet and OIF/CEI standards offer an increasing challenge for PCB designers on multiple fronts. On the one hand, the speeds are approximately doubling for each generation. At the same time, the circuit board material used is often the same as the previous generations in order to keep costs down. To compensate for the increased loss at higher data rates, complex equalization techniques are employed.
From an IC design perspective, deciding what types of equalization circuits need to be incorporated in the transceivers design, has cost, power, and silicon area implications. From an EDA perspective, the large variety of compliance methods and ways to define equalization types along with their associated transfer functions and constraints leads to increased complexity of the analysis tools.
This Siemens paper will highlight some important aspects of the most popular interconnect specifications, with a focus on the reference equalizers.
To download this free white paper, click here.